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DATA SHEET
MOS INTEGRATED CIRCUIT
PD784054(A)
16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The PD784054(A) is a product of the 78K/IV series, and based on the PD784044(A) with the real-time output function and two units of timers/counters deleted and a standby function invalid mode provided. A stricter quality assurance program applies to the PD784054(A) compared to the PD784054 (standard model). The PD784054(A) is provided with many peripheral hardware functions such as ROM, RAM, I/O port, 10-bit resolution A/D converter, timer, serial interface, and interrupt functions, in addition to a high-speed, high-performance CPU. Moreover, a flash memory model, PD78F4046Note, that can operate on the same supply voltage as the mask ROM model, and many development tools are under development. Note Use for functional evaluation only. The functions are described in detail in the following User's Manuals. Be sure to read these manuals when designing your system.
PD784054 User's Manual - Hardware
: U11719E
78K/IV Series User's Manual - Instruction : U10905E
FEATURES
* Higher reliability compared to the PD784054 * Minimum instruction execution time * I/O port * Timer * A/D converter * Watchdog timer * Supply voltage : 160 ns (with 12.5-MHz internal clock) *** PD784054(A) 200 ns (with 10-MHz internal clock) *** PD784054(A1), (A2) : 64 lines : 16-bit timer x 3 units : 10-bit resolution x 16 channels : 1 channel : VDD = 4.5 to 5.5 V
* Serial interface UART/IOE (3-wire serial I/O) : 2 channels * Standby function HALT/STOP/IDLE/standby function invalid mode
APPLICATION FIELDS
Automotive appliances, etc. In this document, in addition to the PD784054(A), the PD784054(A1) and 784054(A2) are also explained. However, unless otherwise specified, the PD784054(A) is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Document No. U13122EJ1V0DS00 (1st edition) Date Published January 1998 N CP(K) Printed in Japan
(c)
1998
PD784054(A)
ORDERING INFORMATION
Part Number Package 80-pin plastic QFP (14 x 14 mm) 80-pin plastic QFP (14 x 14 mm) 80-pin plastic QFP (14 x 14 mm) Internal ROM (bytes) Internal RAM (bytes) 32 K 32 K 32 K 1024 1024 1024
PD784054GC(A)-xxx-3B9 PD784054GC(A1)-xxx-3B9 PD784054GC(A2)-xxx-3B9
Remark xxx indicates ROM code suffix. QUALITY GRADE Special
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Differences between PD784054 and PD784054(A)
Part Number Item Quality grade Operating ambient temperature (TA) Operating frequency Minimum instruction execution time DC characteristics AC characteristics A/D converter characteristics Standard -10 to + 70C 8 to 32 MHz 125 ns (with 16-MHz internal clock) VDD supply current differs. Bus timing and serial operation differ. Conversion time and sampling time differ.
PD784054
Special
PD784054(A)
-40 to +85 C 8 to 25 MHz 160 ns (with 12.5-MHz internal clock)
Differences between PD784054(A), 784054(A1) and 784054(A2)
Part Number Item Operating ambient temperature (TA) Operating frequency Minimum instruction execution time DC characteristics AC characteristics A/D converter characteristics
PD784054(A)
-40 to +85 C 8 to 25 MHz 160 ns (with 12.5-MHz internal clock)
PD784054(A1)
-40 to +110 C 8 to 20 MHz 200 ns (with 10-MHz internal clock)
PD784054(A2)
-40 to +125 C
Analog pin input leakage current, VDD supply current and data retention current differ. Bus timing and serial operation differ. AVREF current and A/D converter data retention current differ.
2
PD784054(A)
Product Development of 78K/IV Series
: Under mass production : Under development
Standard models
For I2C bus
For multimaster I2C bus
PD784038Y PD784038
Improved internal memory capacity, pin compatible with PD784026 For multimaster I2C bus
PD784225Y PD784225
80 pins, ROM correction added For multimaster I2C bus
PD784026
A/D, 16-bit timer, improved power management
PD784216Y PD784216
100 pins, I/O, improved internal memory capacity
PD784218Y PD784218
Improved internal memory capacity, ROM correction added
PD784054
PD784046
Internal 10-bit A/D ASSP models
PD784955
For DC converter control
PD784908
Internal IEBusTM controller For multimaster I2C bus
PD78F4943
For CD-ROM Flash memory 56 KB
PD784928Y PD784928
Improved functions of PD784915
PD784915
Software servo control, internal analog circuit for VCR, improved timer
3
PD784054(A)
FUNCTION LIST
Item Number of basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space I/O port Total Input I/O ROM RAM 113 8 bits x 16 registers x 8 banks, or 16 bits x 8 registers x 8 banks (memory mapping) * 160 ns (with internal 12.5-MHz clock): PD784054(A) * 200 ns (with internal 10-MHz clock) : PD784054(A1), (A2) 32K bytes 1024 bytes 1M bytes with program/data combined 64 pins 17 pins 47 pins Function
Pins with Pins with 29 pins ancillary pull-up functions Note resistors Timer Timer 0 (16 bits) Timer 1 (16 bits) Timer 4 (16 bits) A/D converter Serial interface Watchdog timer Interrupt : Timer register x 1, capture/compare register x 4 : Timer register x 1, compare register x 2 : Timer register x 1, compare register x 2 Pulse output possible * Toggle output * Set/reset output Pulse output possible * Toggle output * Set/reset output
10-bit resolution x 16 channels UART/IOE (3-wire serial I/O): 2 channels (with baud rate generator) 1 channel
Hardware source 23 (internal: 19, external: 8 (internal/external: 4)) Software source Non-maskable Maskable BRK instruction, BRKCS instruction, operand error Internal: 1, external: 1 Internal: 18, external: 7 (internal/external: 4) * 4 levels of programmable priorities * 3 processing formats: vectored interrupt/macro service/context switching
Bus sizing Standby Supply voltage Package
8-bit/16-bit external data bus width selectable HALT/STOP/IDLE/standby function invalid mode VDD = 4.5 to 5.5 V 80-pin plastic QFP (14 x 14 mm)
Note
The pins with ancillary functions are included in the I/O pins.
4
PD784054(A)
CONTENTS
1. DIFFERENCES BETWEEN PD784054(A) AND PD784044(A), 784046(A) ................................. 7 2. PIN CONFIGURATION (Top View) ..................................................................................................... 8 3. SYSTEM CONFIGURATION EXAMPLE ...........................................................................................10 4. BLOCK DIAGRAM ............................................................................................................................. 11 5. PIN FUNCTIONS ................................................................................................................................12
5.1 5.2 5.3 Port Pins .................................................................................................................................................... 12 Pins Other Than Port Pins ...................................................................................................................... 14 I/O Circuits of Pins and Processing of Unused Pins .......................................................................... 16
6. CPU ARCHITECTURE .......................................................................................................................18
6.1 6.2 Memory Space .......................................................................................................................................... 18 CPU Registers ........................................................................................................................................... 20 6.2.1 6.2.2 6.2.3 General-purpose registers ............................................................................................................. 20 Control registers ............................................................................................................................. 21 Special function registers (SFRs) .................................................................................................. 22
7. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................27
7.1 7.2 7.3 7.4 7.5 7.6 7.7 Ports ........................................................................................................................................................... 27 Clock Generation Circuit ......................................................................................................................... 28 Timer .......................................................................................................................................................... 30 A/D Converter ........................................................................................................................................... 32 Serial Interface .......................................................................................................................................... 33 7.5.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ....................................................... 34 Edge Detection Circuit ............................................................................................................................ 36 Watchdog Timer ........................................................................................................................................ 36
8. INTERRUPT FUNCTION....................................................................................................................37
8.1 8.2 8.3 8.4 Interrupt Source ....................................................................................................................................... 37 Vectored Interrupt .................................................................................................................................... 39 Context Switching .................................................................................................................................... 40 Macro Service ........................................................................................................................................... 41
9. LOCAL BUS INTERFACE .................................................................................................................44
9.1 9.2 9.3 9.4 Memory Expansion .................................................................................................................................. 45 Memory Space .......................................................................................................................................... 46 Programmable Wait .................................................................................................................................. 46 Bus Sizing Function ................................................................................................................................. 46
5
PD784054(A)
10. STANDBY FUNCTION .......................................................................................................................47 11. RESET FUNCTION ............................................................................................................................48 12. INSTRUCTION SET ...........................................................................................................................49 13. ELECTRICAL SPECIFICATIONS ......................................................................................................54 14. PACKAGE DRAWING .......................................................................................................................77 15. RECOMMENDED SOLDERING CONDITIONS ................................................................................78 APPENDIX A. DEVELOPMENT TOOLS ................................................................................................79 APPENDIX B. RELATED DOCUMENTS ...............................................................................................82
6
PD784054(A)
1. DIFFERENCES BETWEEN PD784054(A) AND PD784044(A), 784046(A)
Table 1-1 shows the differences between the PD784054(A) and PD784044(A), 784046(A). Table 1-1. Differences between PD784054(A) and PD784044(A), 784046(A)
Part Number Item Internal ROM Internal RAM Port 1 Real-time output port Timer/counter Standby function
PD784054(A)
32K bytes (mask ROM) 1024 bytes P10-P12 None 16-bit timer x 3 units HALT/STOP/IDLE/ standby function invalid mode Provided 23
PD784044(A)
PD784046(A)
64K bytes (mask ROM) 2048 bytes
P10-P13 4 bits x 1 16-bit timer/counter x 2 units 16-bit timer x 3 units HALT/STOP/IDLE mode
MODE1 pin Interrupt hardware source
Not provided 27
7
PD784054(A)
2. PIN CONFIGURATION (Top View)
* 80-pin plastic QFP (14 x 14 mm)
PD784054GC(A)-xxx-3B9, 784054GC(A1)-xxx-3B9, 784054GC(A2)-xxx-3B9
P24/INTP3/TO03
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 AVREF AVDD VSS VDD P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P22/INTP1/TO01 BWD P21/INTP0/TO00 MODE P20/NMI VSS VDD MODE1 P12 P11 P10 P03 P02 P01 P00 P37/ASCK2/SCK2 P36/TxD2/SO2 P35/RxD2/SI2 P34/ASCK/SCK1 P33/TxD/SO1
P30/TO10
P31/TO11
Cautions 1. Directly connect the MODE pin to VSS. 2. Usually, directly connect the MODE1 pin to VSS.
8
P32/RxD/SI1
P52/AD10
P53/AD11
P54/AD12
P55/AD13
P56/AD14
P57/AD15
P60/A16
P61/A17
P62/A18
P63/A19
P93/ASTB
P90/RD
P92/HWR
P50/AD8
P51/AD9
P91/LWR
P94/WAIT
P23/INTP2/TO02
P27/INTP6
P26/INTP5
P25/INTP4
P87/ANI15
P86/ANI14
P85/ANI13
P84/ANI12
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
CLKOUT
RESET
AVSS
VDD
VSS
X2
X1
PD784054(A)
A16-A19 AD0-AD15 ANI0-ANI15 ASCK, ASCK2 ASTB AVDD AVREF AVSS BWD CLKOUT HWR INTP0-INTP6 LWR MODE, MODE1 NMI P00-P03 P10-P12 P20-P27 P30-P37 : Address Bus : Address/Data Bus : Analog Input : Asynchronous Serial Clock : Address Strobe : Analog Power Supply : Analog Reference Voltage : Analog Ground : Bus Width Definition : Clock Out : High Address Write Strobe : Interrupt from Peripherals : Low Address Write Strobe : Mode : Non-maskable Interrupt : Port0 : Port1 : Port2 : Port3 P40-P47 P50-P57 P60-P63 P70-P77 P80-P87 P90-P94 RD RESET RxD, RxD2 SCK1,SCK2 SI1, SI2 SO1, SO2 TxD, TxD2 VDD VSS WAIT X1, X2 : Port4 : Port5 : Port6 : Port7 : Port8 : Port9 : Read Strobe : Reset : Receive Data : Serial Clock : Serial Input : Serial Output : Transmit Data : Power Supply : Ground : Wait : Crystal
TO00-TO03, TO10, TO11 : Timer Output
9
PD784054(A)
3. SYSTEM CONFIGURATION EXAMPLE
Display lamp ABS control unit
PD784054(A)
Output interface
Subthrottle control
Pulse * Right front wheel speed * Left front wheel speed * Right rear wheel speed * Left rear wheel speed Digital quantity * Brake sw * Parking sw * Neutral sw * TCS cut sw, etc.
CPU
Generalpurpose I/O
Solenoid drive circuit Monitor circuit Input interface External I/O interface
Input interface
Generalpurpose I/O
ROM: 32 KB RAM : 1 KB 10-bit A/D converter
Solenoid * Right front wheel * Left front wheel * Right rear wheel * Left rear wheel
* Timer unit * Interrupt controller
Analog quantity * G sensor (front, rear) * G sensor (left, right) * Throttle divergence * Rupture detection, etc. External tester display system
Serial I/O
UART
Microcomputer for monitor Battery voltage (12 V) Power unit
10
PD784054(A)
4. BLOCK DIAGRAM
BWD AD0-AD15 A16-A19 RD LWR, HWR ASTB WAIT P00-P03
NMI INTP0-INTP6
Programmable interrupt controller
BUS I/F
INTP0-INTP3 TO00-TO03
Timer 0 (16 bits) Port 0 Timer 1 (16 bits)
TO10, TO11
Port 1
P10-P12 P20 P21-P27 P30-P37
Port 2 Timer 4 (16 bits) 78K/IV CPU core ROM Port 3
ANI0-ANI15 AVDD AVSS AVREF INTP4 A/D converter
Port 4
P40-P47
Port 5
P50-P57
Port 6 RAM Watchdog timer Port 7
P60-P63
P70-P77
RxD/SI1 TxD/SO1 ASCK/SCK1
Port 8 UART/IOE1 Baud-rate generator Port 9
P80-P87
P90-P94 CLKOUT RESET MODE MODE1 X1 X2 VDD VSS
RxD2/SI2 TxD2/SO2 ASCK2/SCK2
UART/IOE2 Baud-rate generator
System control
11
PD784054(A)
5. PIN FUNCTIONS 5.1 Port Pins (1/2)
Pin Name P00-P03 I/O I/O Shared by: - Function Port 0 (P0): * 4-bit I/O port * Can be set in input/output mode bit-wise. * Pins in input mode can all be connected to pull-up resistors at once via software. Port 1 (P1): * 3-bit I/O port * Can be set in input/output mode bit-wise. Port 2 (P2): * 8-bit I/O port Input only Can be set in input/output mode bit-wise.
P10-P12
I/O
-
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40-P47
Input I/O
NMI INTP0/TO00 INTP1/TO01 INTP2/TO02 INTP3/TO03 INTP4 INTP5 INTP6
I/O
TO10 TO11 RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2
Port 3 (P3): * 8-bit I/O port * Can be set in input/output mode bit-wise.
I/O
AD0-AD7
Port 4 (P4): * 8-bit I/O port * Can be set in input/output mode bit-wise. * Pins in input mode can all be connected to pull-up resistors at once via software. Port 5 (P5): * 8-bit I/O port * Can be set in input/output mode bit-wise. * Pins in input mode can all be connected to pull-up resistors at once via software. Port 6 (P6): * 4-bit I/O port * Can be set in input/output mode bit-wise. * Pins in input mode can all be connected to pull-up resistors at once via software.
P50-P57
I/O
AD8-AD15
P60-P63
I/O
A16-A19
12
PD784054(A)
5.1 Port Pins (2/2)
Pin Name P70-P77 P80-P87 P90 P91 P92 P93 P94 I/O Input Input I/O Shared by: ANI0-ANI7 ANI8-ANI15 RD LWR HWR ASTB WAIT Port 7 (P7): * 8-bit input port Port 8 (P8): * 8-bit input port Port 9 (P9): * 5-bit I/O port * Can be set in input/output mode bit-wise. * Pins in input mode can all be connected to pull-up resistors at once via software. Function
13
PD784054(A)
5.2 Pins Other Than Port Pins (1/2)
Pin Name NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 TO00 TO01 TO02 TO03 TO10 TO11 RxD RxD2 TxD TxD2 ASCK ASCK2 SI1 SI2 SO1 SO2 SCK1 SCK2 AD0-AD7 AD8-AD15 Note I/O I/O I/O Output Input Input Output Input Output I/O Input Shared by: P20 P21/TO00 P22/TO01 P23/TO02 P24/TO03 P25 P26 P27 P21/INTP0 P22/INTP1 P23/INTP2 P24/INTP3 P30 P31 P32/SI1 P35/SI2 P33/SO1 P36/SO2 P34/SCK1 P37/SCK2 P32/RxD P35/RxD2 P33/TxD P36/TxD2 P34/ASCK P37/ASCK2 P40-P47 P50-P57 Serial data input (UART0) Serial data input (UART2) Serial data output (UART0) Serial data output (UART2) Baud rate clock input (UART0) Baud rate clock input (UART2) Serial data input (3-wire serial I/O1) Serial data input (3-wire serial I/O2) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial clock input/output (3-wire serial I/O1) Serial clock input/output (3-wire serial I/O2) Lower multiplexed address/data bus when external memory is connected * When 8-bit bus is specified Higher address bus when external memory is connected * When external 16-bit bus is specified Higher multiplexed address/data bus when external memory is connected Higher address bus when external memory is connected Read strobe to external memory * When external 8-bit bus is specified Write strobe to external memory * When external 16-bit bus is specified Write strobe to external memory located at lower position Write strobe to external memory located at higher position when external 16-bit bus is specified Timing signal output to externally latch address information output from AD0 through AD15 pins to access external memory Timer output Function Non-maskable interrupt request input External interrupt request input Capture trigger signal of CC00 Capture trigger signal of CC01 Capture trigger signal of CC02 Capture trigger signal of CC03 Conversion start trigger input of A/D converter -
A16-A19 Note RD LWR
Output Output Output
P60-P63 P90 P91
HWR ASTB Output
P92 P93
Note
The number of pins used as address bus pins differs depending on the external address space (refer to 9. LOCAL BUS INTERFACE).
14
PD784054(A)
5.2 Pins Other Than Port Pins (2/2)
Pin Name WAIT BWD MODE MODE1 CLKOUT X1 X2 RESET ANI0-ANI7 ANI8-ANI15 AVREF AVDD AVSS VDD VSS - I/O Input Input Input Input Output Input - Input Input Shared by: P94 - - - - - - - P70-P77 P80-P87 - - - - - Reference voltage for A/D converter Positive power supply for A/D converter GND for A/D converter Positive power supply GND Chip reset Analog voltage input for A/D converter Inserts wait. Sets bus width. Directly connect this pin to VSS (this pin specifies test mode of IC). Specifies standby function invalid mode. Usually, connect this pin to VSS. Clock output. Outputs low level during IDLE mode and STOP mode. Otherwise, always outputs fXX (oscillation frequency). Connect crystal for system clock oscillation (clock can be also input to X1). Function
15
PD784054(A)
5.3 I/O Circuits of Pins and Processing of Unused Pins
Table 5-1 shows the I/O circuit type of each pin and recommended processing of the unused pins. For the I/O circuit type, refer to Figure 5-1. Table 5-1. I/O Circuit Type of Each Pin and Recommended Processing of Unused Pins
Pin Name P00-P03 P10-P12 P20/NMI P21/INTP0/TO00 P22/INTP1/TO01 P23/INTP2/TO02 P24/INTP3/TO03 P25/INTP4 P26/INTP5 P27/INTP6 P30/TO10 P31/TO11 P32/RxD/SI1 P33/TxD/SO1 P34/ASCK/SCK1 P35/RxD2/SI2 P36/TxD2/SO2 P37/ASCK2/SCK2 P40/AD0-P47/AD7 P50/AD8-P57/AD15 P60/A16-P63/A19 P70/ANI0-P77/ANI7 P80/ANI8-P87/ANI15 P90/RD P91/LWR P92/HWR P93/ASTB P94/WAIT MODE,MODE1 RESET CLKOUT AVREF AVSS AVDD Connect to VDD. 1 2 3 - Output - Leave unconnected. Connect to VSS. Input Directly connect to VSS. - 5-A I/O Input: Individually connect to VDD or VSS via resistor. Output: Leave unconnected. 9 Input Connect to VSS. 8 5-A 8 5 5 I/O Circuit Type 5-A 5 2 8 Input I/O I/O I/O Recommended Connection of Unused Pins Input: Individually connect to VDD or VSS via resistor. Output: Leave unconnected. Connect to VSS. Input: Individually connect to VDD or VSS via resistor. Output: Leave unconnected.
Remark The circuit type numbers are serial in the 78K series but are not always so with some models (because some models are not provided with particular circuits).
16
PD784054(A)
Figure 5-1. I/O Circuits of Pins
Type 1
Type 5-A
VDD
VDD P-ch IN
Pullup Enable Data
P-ch VDD P-ch IN/OUT
N-ch
Output disable Input enable
N-ch
Type 2
Type 8
VDD Data IN Output disable N-ch P-ch IN/OUT
Schmitt trigger input with hysteresis characteristics Type 3 Type 9
VDD IN P-ch OUT N-ch
P-ch N-ch
Comparator
+ -
VREF (Threshold voltage)
Input enable
Type 5 VDD Data P-ch IN/OUT Output disable N-ch
Input enable
17
PD784054(A)
6. CPU ARCHITECTURE 6.1 Memory Space
A 1M-byte memory space can be accessed. The mapping of the internal data area (special function registers and internal RAM) can be selected by using the LOCATION instruction. The LOCATION instruction must be always executed after the reset signal has been deasserted, and must not be used more than once. (1) When LOCATION 0 instruction is executed * Internal memory The internal data area and internal ROM area are mapped as follows: Internal data area : 0FB00H through 0FFFFH Internal ROM area : 00000H through 07FFFH * External memory The external memory is accessed in the external memory expansion mode. (2) When LOCATION 0FH instruction is executed * Internal memory The internal data area and internal ROM area are mapped as follows: Internal data area : 0FB00H through FFFFFH Internal ROM area : 00000H through 07FFFH * External memory The external memory is accessed in the external memory expansion mode.
18
PD784054(A)
Figure 6-1. Memory Map
When LOCATION 0 instruction is executed
F F F F FH 0 F E F FH External memory Note 1 (960K bytes) 0 FE 8 0H 0 F E 7 FH 0 FE 3 7H 0 FE 0 6H Main RAM Peripheral RAM 0 FD 0 0 H 0 F C F FH Program/data area (512 bytes) 0 FB 0 0H 0 7 F F FH
Note 2
When LOCATION 0FH instruction is executed
F F F F F H Special function registers (SFRS) F F F D F H Note 1 F F FD 0H (256 bytes) FFF 0 0H
F F E F FH General-purpose registers (128 bytes) F FE 8 0H F F E 7 FH F FE 3 7H F FE 0 6H F FD 0 0 H F F C F FH
F F E F FH F FB 0 0H F FA F FH
Internal RAM (1K bytes) Cannot be used (1280 bytes)
F F 6 0 0H F F 5 F FH
1 0 0 0 0H 0 F F F F H Special function registers (SFRs) 0 F F D F H Note 1 0 F FD 0 H (256 bytes) 0 F F 0 0H 0 F E F FH Internal memory (1K bytes) 0 FB 0 0H 0 FA F FH Cannot be used (1280 bytes) 0 F 6 0 0H 0 F 5 F FH
Macro service control word area (50 bytes) Data area (512 bytes)
F FB 0 0H
External memoryNote 1 (1013248 bytes)
Program/data area (32K bytes) 0 1 0 0 0H 0 0 F F FH CALLF entry area (2K bytes) 1 0 0 0 0H 0 F F F FH 0 8 0 0 0H 0 7 F F FH
Note 2
External memory Note 1 (30208 bytes)
0 8 0 0 0H 0 7 F F FH
0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH 0 0 0 0 0H
Internal ROM (32K bytes)
CALLT table area (64 bytes) Vector table area (64 bytes)
Internal ROM (32K bytes)
0 0 0 0 0H
0 0 0 0 0H
Notes 1. Accessed in the external memory expansion mode. 2. Base area or entry area by reset or interrupt. The internal RAM is not reset.
19
PD784054(A)
6.2 CPU Registers
6.2.1 General-purpose registers Sixteen 8-bit general-purpose registers are provided. Two 8-bit general-purpose registers can be used in pairs as a 16-bit general-purpose register. Of the 16-bit registers, four can be used with an 8-bit register for address expansion as 24-bit address specification registers. Eight banks of register sets are available which can be selected by software or context switching function. The general-purpose registers except the V, U, T, and W registers for address expansion are mapped to the internal RAM. Figure 6-2. General-Purpose Register Format
A(R1) AX(RP0) B(R3) BC(RP1) R5 RP2 R7 RP3 V VVP(RG4) U UUP(RG5) T D(R13) TDE(RG6) W H(R15) WHL(RG7) HL(RP7) DE(RP6) R11 UP(RP5) R9 VP(RP4)
X(R0) C(R2) R4 R6 R8
R10
E(R12)
L(R14)
8 banks
( ): absolute name
Caution
R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers, respectively, by setting the RSS bit of the PSW to 1. However, use this function only when using a 78K/III series program.
20
PD784054(A)
6.2.2 Control registers (1) Program counter (PC) This is a 20-bit program counter. Its contents are automatically updated as the program is executed. Figure 6-3. Program Counter (PC) Format
19 PC
0
(2) Program status word (PSW) This register retains the status of the CPU and its contents are automatically updated as the program is executed. Figure 6-4. Program Status Word (PSW) Format
15 PSWH PSW 7 PSWL S UF
14 RBS2
13 RBS1
12 RBS0
11 --
10 --
9 --
8 --
6 Z
5 RSS
Note
4 AC
3 IE
2 P/V
1 0
0 CY
Note
This flag is provided so that the PD784054(A) maintains compatibility with the 78K/III series. Be sure to clear this flag to 0 when using 78K/III series software.
(3) Stack pointer (SP) This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the high-order 4 bits of this pointer. Figure 6-5. Stack Pointer (SP) Format
23 SP 0 0 0
20 0
0
21
PD784054(A)
6.2.3 Special function registers (SFRs) The special function registers are registers to which special functions are assigned, and include the mode registers and control registers of the internal peripheral hardware. These registers are mapped to a 256-byte space of addresses 0FF00H through 0FFFFHNote. Note When the LOCATION 0 instruction is executed. FFF00H through FFFFFH when the LOCATION 0FH instruction is executed. Caution Do not access an address in this area to which no SFR is allocated. If an address to which no SFR is allocated is accessed by mistake, the PD784054(A) may be deadlocked. The deadlock status can be cleared only by inputting the reset signal. Table 6-1 lists the special function registers. The meanings of the symbols in this table are as follows: * Symbol ................................. Symbol indicating an SFR. These symbols are reserved for an NEC's assembler (RA78K4). With a C compiler (CC78K4), they can be used as sfr variables by using the #pragma sfr directive. * R/W ...................................... Indicates whether the corresponding SFR can be read/written. R/W : Read/write R W : Read only : Write only
* Bit units for manipulation .... Indicates bit units in which the corresponding SFR can be manipulated. SFRs that can be manipulated in 16-bit units can be written as operand sfrp. Specify the even addresses of these SFRs when specifying an address. SFRs that can be manipulated bit-wise can be written in bit manipulation instructions. * On reset ............................... Indicates the status of each register when the RESET signal is input.
22
PD784054(A)
Table 6-1. Special Function Register List (1/4)
Address Note 1 Special Function Register (SFR) Name Symbol R/W Bit units for manipulation 1 bit 0FF00H 0FF01H 0FF02H 0FF03H 0FF04H 0FF05H 0FF06H 0FF07H 0FF08H 0FF09H 0FF10H 0FF11H 0FF12H 0FF13H 0FF14H 0FF15H 0FF16H 0FF17H 0FF18H 0FF19H 0FF1AH 0FF1BH 0FF1CH 0FF1DH 0FF1EH 0FF1FH 0FF20H 0FF21H 0FF22H 0FF23H 0FF24H 0FF25H 0FF26H 0FF29H 0FF2FH 0FF30H 0FF31H Port 0 mode register Port 1 mode register Port 2 mode register Port 3 mode register Port 4 mode register Port 5 mode register Port 6 mode register Port 9 mode register Port read control register Timer unit mode register 0 Timer mode control register PM0 PM1 PM2 Note 3 PM3 PM4 PM5 PM6 PM9 PRDC TUM0 TMC - - - - - - - - - - - 00H FFH Compare register 11 CM11 - - Compare register 10 CM10 R/W - - Undefined Timer register 1 TM1 R - - 0000H Capture/compare register 03 CC03 - - Capture/compare register 02 CC02 - - Capture/compare register 01 CC01 - - Capture/compare register 00 CC00 R/W - - Undefined Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Timer register 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 TM0 R/W R - - R
Note 2
On reset
8 bits
16 bits - - - - - - - - - - 0000H Undefined
R/W
R/W
Notes 1. When the LOCATION 0 instruction is executed. Add "F0000H" to this value when the LOCATION 0FH instruction is executed. 2. Bit 0 of P2 can only be read. Bits 1 through 7 can be read/written. 3. Bit 0 of PM2 is fixed to "1" by hardware.
23
PD784054(A)
Table 6-1. Special Function Register List (2/4)
Address Note 1 Special Function Register (SFR) Name Symbol R/W Bit units for manipulation 1 bit 0FF32H 0FF33H 0FF37H 0FF38H 0FF3AH 0FF3BH 0FF3CH 0FF3DH 0FF3EH 0FF3FH 0FF42H 0FF43H 0FF49H 0FF4EH 0FF4FH 0FF60H 0FF61H 0FF62H 0FF63H 0FF64H 0FF65H 0FF6EH 0FF70H 0FF71H 0FF71H 0FF72H 0FF73H 0FF73H 0FF74H 0FF75H 0FF75H 0FF76H 0FF77H 0FF77H 0FF78H 0FF79H 0FF79H A/D conversion result register 4H ADCR4H - - A/D conversion result register 3H A/D conversion result register 4 ADCR3H ADCR4 - - - - A/D conversion result register 2H A/D conversion result register 3 ADCR2H ADCR3 - - - - A/D conversion result register 1H A/D conversion result register 2 ADCR1H ADCR2 - - - - A/D conversion result register 0H A/D conversion result register 1 ADCR0H ADCR1 - - - - A/D converter mode register A/D conversion result register 0 ADM ADCR0 R - - - 00H Undefined Compare register 41 CM41 - - Compare register 40 CM40 R/W - - Undefined Timer output control register 0 Timer output control register 1 Timer mode control register 4 Prescaler mode register Prescaler mode register 4 Noise protection control register External interrupt mode register 0 External interrupt mode register 1 Interrupt valid edge flag register 1 Interrupt valid edge flag register 2 Port 2 mode control register Port 3 mode control register Port 9 mode control register Pull-up resistor option register L Pull-up resistor option register H Timer register 4 TOC0 TOC1 TMC4 PRM PRM4 NPC INTM0 INTM1 IEF1 IEF2 PMC2 Note 2 PMC3 PMC9 PUOL PUOH TM4 R - - - - R/W 8 bits 16 bits - - - - - - - - - - - - - - - 0000H 00H Undefined 00H On reset
Notes 1. When the LOCATION 0 instruction is executed. Add "F0000H" to this value when the LOCATION 0FH instruction is executed. 2. Bits 0, and 5 through 7 of PMC2 are fixed to "0" by hardware.
24
PD784054(A)
Table 6-1. Special Function Register List (3/4)
Address Note 1 Special Function Register (SFR) Name Symbol R/W Bit units for manipulation 1 bit 0FF7AH 0FF7BH 0FF7BH 0FF7CH 0FF7DH 0FF7DH 0FF7EH 0FF7FH 0FF7FH 0FF84H 0FF85H 0FF88H 0FF89H 0FF8AH 0FF8BH 0FF8CH A/D conversion result register 7H Clocked serial interface mode register 1 Clocked serial interface mode register 2 Asynchronous serial interface mode register Asynchronous serial interface mode register 2 ADCR7H CSIM1 CSIM2 ASIM ASIM2 R R/W - - - - - - - - - W R/W R W R/W - - - - - - - R R/W - - - - - - - - - - - - - 80H FFH FFFFH 00H Undefined 00H A/D conversion result register 6H A/D conversion result register 7 ADCR6H ADCR7 - - - - A/D conversion result register 5H A/D conversion result register 6 ADCR5H ADCR6 - - - - A/D conversion result register 5 ADCR5 R - 8 bits - 16 bits Undefined On reset
Asynchronous serial interface status register ASIS Asynchronous serial interface status register 2 Serial receive buffer: UART0 Serial transmit shift register: UART0 Serial shift register: IOE1 ASIS2 RXB TXS SIO1 RXB2 TXS2 SIO2 BRGC BRGC2 ISPR IMC MK0L MK0
0FF8DH
Serial receive buffer: UART2 Serial transmit shift register: UART2 Serial shift register: IOE2
0FF90H 0FF91H 0FFA8H 0FFAAH 0FFACH 0FFACH 0FFADH 0FFADH 0FFAEH 0FFAEH 0FFAFH 0FFAFH 0FFC0H 0FFC2H 0FFC4H 0FFC7H
Baud rate generator control register Baud rate generator control register 2 In-service priority register Interrupt mode control register Interrupt mask register 0L Interrupt mask register 0
Interrupt mask register 0H Interrupt mask register 1L Interrupt mask register 1
MK0H MK1L MK1 - -
- -
FFH
FFFFH
Interrupt mask register 1H Standby control registerNote 2 register Note 2
MK1H STBC WDM MM PWC1 - - -
- - - - -
FFH 30H 00H 20H AAH
Watchdog timer mode
Memory expansion mode register Programmable wait control register 1
Notes 1. When the LOCATION 0 instruction is executed. Add "F0000H" to this value when the LOCATION 0FH instruction is executed. 2. These registers can be written only by using dedicated instructions MOV STBC, #byte and MOV WDM, #byte, and cannot be written by any other instructions.
25
PD784054(A)
Table 6-1. Special Function Register List (4/4)
Address Note 1 Special Function Register (SFR) Name Symbol R/W Bit units for manipulation 1 bit 0FFC8H 0FFC9H 0FFCAH 0FFCBH 0FFCFH 0FFD0H0FFDFH 0FFE0H 0FFE1H 0FFE2H 0FFE3H 0FFE4H 0FFE5H 0FFE6H 0FFE7H 0FFE8H 0FFE9H 0FFEAH 0FFEBH 0FFF0H 0FFF1H 0FFF2H 0FFF3H Oscillation stabilization time specification register OSTS External SFR area Interrupt control register (INTOV0) Interrupt control register (INTOV1) Interrupt control register (INTOV4) Interrupt control register (INTP0) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3) Interrupt control register (INTP4) Interrupt control register (INTP5) Interrupt control register (INTP6) Interrupt control register (INTCM10) Interrupt control register (INTCM11) Interrupt control register (INTCM40) Interrupt control register (INTCM41) Interrupt control register (INTSER) Interrupt control register (INTSR) Interrupt control register (INTCSI1) 0FFF4H 0FFF5H 0FFF6H Interrupt control register (INTST) Interrupt control register (INTSER2) Interrupt control register (INTSR2) Interrupt control register (INTCSI2) 0FFF7H 0FFF8H Interrupt control register (INTST2) Interrupt control register (INTAD) - OVIC0 OVIC1 OVIC4 PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 CMIC10 CMIC11 CMIC40 CMIC41 SERIC SRIC CSIIC1 STIC SERIC2 SRIC2 CSIIC2 STIC2 ADIC - - - - - - - - - - - - - - - - - - - - - - - - - - 00H Undefined 43H Bus width specification register BW - - Note 2 Programmable wait control register 2 PWC2 R/W - 8 bits - 16 bits AAAAH On reset
Notes 1. When the LOCATION 0 instruction is executed. Add "F0000H" to this value when the LOCATION 0FH instruction is executed. 2. The value of this register differs on reset depending on the setting of the BWD pin. BWD = 0: 0000H BWD = 1: 00FFH
26
PD784054(A)
7. PERIPHERAL HARDWARE FUNCTIONS 7.1 Ports
The PD784054(A) has the ports shown in Figure 7-1. These ports can be used for various control operations. The function of each port is shown in Table 7-1. Ports 0, 4 through 6, and 9 can be connected to an internal pull-up resistor via software when they are set in the input mode. Figure 7-1. Port Configuration
P00 Port 0 P03 P10 Port 1 P12 P20
P50
Port 5
P57 P60 Port 6
Port 2
P63
P27 P30 P70-P77 8 Port 7
Port 3
P37 P40 P80-P87 8 Port 8
Port 4 P90 P47 P94 Port 9
27
PD784054(A)
Table 7-1. Port Function
Port Name Port 0 Port 1 Port 2 Pin Name P00-P03 P10-P12 P20-P27 Can be set in input or output mode bit-wise (however, P20 is input-only). Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 P30-P37 P40-P47 P50-P57 P60-P63 P70-P77 P80-P87 P90-P94 Can be set in input or output mode bit-wise. All pins in input mode Input port - Can be set in input or output mode bit-wise. All pins in input mode Function Can be set in input or output mode bit-wise. Specification of Pull-Up Resistor by Software All pins in input mode -
7.2 Clock Generation Circuit
The clock generation circuit generates and controls the internal system clock (CLK) to be supplied to the CPU. Figure 7-2 shows the configuration of this circuit. Figure 7-2. Block Diagram of Clock Generation Circuit
X1 Clock generation circuit X2 fXX or fX
Divider 1/2 fCLK Internal system clock (CLK)
Remark fXX : crystal/ceramic oscillation frequency fX : external clock frequency fCLK : internal system clock frequency
28
PD784054(A)
Figure 7-3. Example of Using Oscillation Circuit (1) Crystal/ceramic oscillation
PD784054(A)
VSS X1
X2
(2) External clock input (a) EXTC bit of OSTS = 1
PD784054(A)
X1
(b) EXTC bit of OSTS = 0
PD784054(A)
X1
PD74HC04, etc.
X2
Leave unconnected
X2
Caution
When using the clock oscillation circuit, wire the portion enclosed by the dotted line in the above figure as follows to avoid adverse effects of wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not extract signals from the oscillation circuit.
29
PD784054(A)
7.3 Timer
The PD784054(A) has three 16-bit timer units. Because a total of 11 interrupt requests are supported, the timer units can be used as 11-channel timers. Table 7-2. Timer Function
Name Item Operation mode Function Interval timer Timer output Toggle output Set/reset output Overflow interrupt Number of interrupt requests 5 3 3 4ch 4ch 2ch 2ch 2ch - - - Timer 0 Timer 1 Timer 4
30
PD784054(A)
Figure 7-4. Block Diagram of Timer Timer 0
fCLK
Prescaler INTP0
Timer register 0 (TM0)
Coinci-
INTOV0 INTCC00 Pulse INTCC01 output control TO00
INTP0
Edge detection INTP1 Edge detection INTP2 Edge detection INTP3 Edge detection
Capter/compare register 00 dence (CC00)
Coinci-
INTP1
Capter/compare register 01 dence (CC01)
Coinci-
TO01 INTCC02 TO02 Pulse INTCC03 output control TO03
INTP2
Capter/compare register 02 dence (CC02)
Coinci-
INTP3
Capter/compare register 03 dence (CC03)
Prescaler: fCLK/4, fCLK/8, fCLK/16, fCLK/32, fCLK/64 Timer 1
Clear control Timer register 1 (TM1)
Coinci-
fCLK
Prescaler
INTOV1 INTCM10 TO10 Pulse output control TO11 INTCM11
Compare register 10 dence (CM10)
Coinci-
Compare register 11 dence (CM11)
Prescaler: fCLK/8, fCLK/16, fCLK/32, fCLK/64, fCLK/128 Timer 4
Clear control Timer register 4 (TM4)
Coinci-
fCLK
Prescaler
INTOV4
Compare register 40 dence (CM40)
Coinci-
INTCM40
Compare register 41 dence (CM41)
INTCM41
Prescaler: fCLK/4, fCLK/8, fCLK/16, fCLK/32, fCLK/64
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PD784054(A)
7.4 A/D Converter
The PD784054(A) has an analog-to-digital (A/D) converter with 16 multiplexed analog input pins (ANI0 through ANI15). This converter is of successive approximation type. The result of conversion is stored to and retained in 10-bit A/D conversion result registers (ADCR0 through ADCR7). Therefore, high-speed, high-accuracy conversion can be performed (conversion time: about 13.5 s: fCLK = 12.5 MHz). The A/D conversion operation can be started in the following modes: * Hardware start : Conversion is started by trigger input (INTP4). * Software start : Conversion is started by setting a bit of the A/D converter mode register (ADM). The A/D converter operates in the following modes: * * Scan mode Select mode : Sequentially selects two or more analog input pins to obtain data to be converted from all the pins. : Selects only one analog input pin to obtain successive conversion values.
The above modes and stopping the conversion are specified by ADM. When the result of conversion is transferred to ADCRn (n = 0 to 7), interrupt request INTAD is generated. By using this interrupt request and by using macro service, the converted value can be successively transferred to memory. Figure 7-5. Block Diagram of A/D Converter
ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15
Input selector Sample & hold circuit
Series resistor string AVREF R/2 Voltage comparator R
Input selector Successive approximation register (SAR) Conversion trigger
Tap selector
R/2 AVSS
INTP4
Edge detection circuit
Control circuit 10
INTAD
Trigger enable
A/D converter mode register (ADM)
8
ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 10 Internal bus
A/D conversion result register
32
PD784054(A)
7.5 Serial Interface
The PD784054(A) is provided with two independent serial interface channels. * Asynchronous serial interface (UART)/3-wire serial I/O (IOE) x 2 By using these serial interface channels, communication with an external device and local communication within a system can be performed at the same time (refer to Figure 7-6). Figure 7-6. Example of Serial Interface
PD784054(A) master
(UART) RS-232C driver/ receiver SO2 RxD TxD Port SI2 SCK2 INTPn Port Note (3-wire serial I/O) SI SO SCK Port INT slave
Note
Handshake line
33
PD784054(A)
7.5.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) Two serial interface channels from which asynchronous serial interface mode and three-wire serial I/O mode can be selected are provided. (1) Asynchronous serial interface mode In this mode, 1-byte data following a start bit is transferred or received. The internal baud rate generator allows communication in a wide range of baud rates. The clock input to the ASCK pin can also be divided to define a baud rate. The baud rate generator can also set a baud rate conforming to the MIDI standard (31.25 kbps). Figure 7-7. Block Diagram in Asynchronous Serial Interface Mode
Internal bus
Receive buffer
RXB, RXB2
RxD, RxD2
Receive shift register
Transmit shift register
TXS, TXS2
TxD, TxD2
Receive control Parity check
INTSR, INTSR2 INTSER, INTSER2
Transmit control Parity append
INTST, INTST2
Baud rate generator
1/2m fCLK ASCK, ASCK2
Selector
1/2n+1 1/2m
Remark fCLK: internal system clock n = 0 to 11 m = 16 to 30
34
PD784054(A)
(2) 3-wire serial I/O mode This mode is to start transmission when the master device makes a serial clock active and to communicate 1-byte data in synchronization with this clock. The interface in this mode communicates with devices that have conventional clocked serial interface. Basically, communication is performed by using three lines: serial clock (SCK) and two serial data (SI and SO) lines. To connect two or more devices, a handshake line is necessary. Figure 7-8. Block Diagram in 3-Wire Serial I/O Mode
Internal bus
Direction control circuit
SIO1, SIO2 SI1, SI2 Shift register Output latch
SO1, SO2
SCK1, SCK2
Serial clock counter
Interrupt generation circuit
INTCSI1, INTCSI2
Serial clock control circuit
Remark fCLK: internal system clock n = 0 to 11 m = 1, 16 to 30
Selector
1/2m
1/2n+1
fCLK
35
PD784054(A)
7.6 Edge Detection Circuit
The interrupt input pins (NMI and INTP0 through INTP6) input not only interrupt requests but also trigger signals of the internal hardware. Because all the interrupts and internal hardware operate by detecting specific edges of the input signals, a function to detect edges is provided. In addition, a noise rejection function is also provided to prevent detection of a wrong edge due to noise.
Pin NMI INTP0-INTP6 Either rising or falling edge Either rising or falling edge, or both edges Detectable Edge Noise Rejected by: Analog delay Clock sampling Note
Note
A sampling clock can be selected.
7.7 Watchdog Timer
A watchdog timer is provided to detect a hang-up of the CPU. This watchdog timer generates a non-maskable interrupt unless it is cleared by software within a specified interval time. Once the watchdog timer has been enable to operate, its operation cannot be stopped by software. Moreover, it can be specified whether the interrupt by the watchdog timer or the interrupt from the NMI pin takes precedence. Figure 7-9. Block Diagram of Watchdog Timer
fCLK/29
fCLK
Divider
fCLK/212 fCLK/213
WDT CLR
36
Selector
fCLK/211
Watchdog timer (8 bits)
Overflow
INTWDT
PD784054(A)
8. INTERRUPT FUNCTION
The three types of interrupt processing shown in Table 8-1 can be selected. Table 8-1. Interrupt Request Processing
Processing Mode Vectored interrupt Context switching Processed by: Software Processing Branches to and executes processing routine (any processing contents). Automatically selects register bank, and branches to and executes processing routine (any processing contents). Firmware Executes data transfer between memory and I/O (any processing contents). Contents of PC and PSW Saves and restores to/from stack. Saves or restores to/from fixed area in register bank. Retained
Macro service
8.1 Interrupt Source
As interrupt sources, twenty-three sources listed in Table 8-2, BRK instruction execution, and operand error are available. Four priority levels of interrupt processing can be selected, so that nesting during interrupt processing and the levels of interrupt requests that are generated at the same time can be controlled. However, nesting always advances with macro service (i.e., nesting is not kept pending). The default priority is the priority (fixed) of the processing for the interrupt requests that have occurred at the same time and have the same priority level (refer to Table 8-2).
37
PD784054(A)
Table 8-2. Interrupt Sources
Type Default Priority Software - Name BRK instruction BRKCS instruction Operand error If result of exclusive OR of operands byte and byte is not FFH when MOV STBC, #byte, MOV WDM, #byte, or LOCATION instruction is executed Detection of pin input edge Overflow of watchdog timer Overflow of timer 0 Overflow of timer 1 Overflow of timer 4 Detection of pin input edge (CC00 capture trigger) Generation of TM0-CC00 coincidence signal Detection of pin input edge (CC01 capture trigger) Generation of TM0-CC01 coincidence signal Detection of pin input edge (CC02 capture trigger) Generation of TM0-CC02 coincidence signal Detection of pin input edge (CC03 capture trigger) Generation of TM0-CC03 coincidence signal Detection of pin input edge (A/D converter conversion start trigger) Detection of pin input edge Detection of pin input edge Generation of TM1-CM10 coincidence signal Generation of TM1-CM11 coincidence signal Generation of TM4-CM40 coincidence signal Generation of TM4-CM41 coincidence signal Occurrence of UART0 reception error End of UART0 reception End of 3-wire serial I/O1 transfer End of UART0 transfer Occurrence of UART2 reception error End of UART2 reception End of 3-wire serial I/O2 transfer End of UART2 transfer End of A/D converter conversion (transfer to ADCR) Internal External Internal External Internal External Internal External Internal External External Internal Source Trigger Execution of instruction Internal/ External - Macro Service -
Nonmaskable Maskable
-
NMI INTWDT
0 (highest) 1 2 3
INTOV0 INTOV1 INTOV4 INTP0 INTCC00
4
INTP1 INTCC01
5
INTP2 INTCC02
6
INTP3 INTCC03
7 8 9 10 11 12 13 14 15
INTP4 INTP5 INTP6 INTCM10 INTCM11 INTCM40 INTCM41 INTSER INTSR INTCSI1
16 17 18
INTST INTSER2 INTSR2 INTCSI2
19 20 (lowest)
INTST2 INTAD
38
PD784054(A)
8.2 Vectored Interrupt
Execution branches to a processing routine by using the memory contents of the vector table address corresponding to an interrupt source as the branch destination address. The following operations are performed so that the CPU processes the interrupt: * On branch : Saves status of CPU (contents of PC and PSW) to stack
* On returning : Restores status of CPU from stack Execution is returned from the processing routine to the main routine by the RETI instruction. The branch destination address must be in a range of 0 to FFFFH. Table 8-3. Vector Table Address
Interrupt Source BRK instruction Operand error NMI INTWDT INTOV0 INTOV1 INTOV4 INTP0 INTCC00 INTP1 INTCC01 INTP2 INTCC02 INTP3 INTCC03 INTP4 0014H 0012H 0010H 000EH Vector Table Address 003EH 003CH 0002H 0004H 0006H 0008H 000AH 000CH Interrupt Source INTP5 INTP6 INTCM10 INTCM11 INTCM40 INTCM41 INTSER INTSR INTCSI1 INTST INTSER2 INTSR2 INTCSI2 INTST2 INTAD 0034H 0036H 002EH 0030H 0032H Vector Table Address 0016H 0018H 001AH 001CH 0026H 0028H 002AH 002CH
39
PD784054(A)
8.3 Context Switching
A specific register bank is selected by hardware when an interrupt request is generated or when the BRKCS instruction is executed. Execution branches to the vector address stored in advance to the selected register bank, and the current contents of the program counter (PC) and program status word (PSW) are stacked to the register bank. The branch destination address must be in a range of 0 to FFFFH. Figure 8-1. Context Switching Operation When Interrupt Request Is Generated
Register bank 0000B < 7 > Transfer Register bank n (n = 0 to 7) PC19-16 PC15_0 < 6 > Exchange < 2 > Save (bits 8 through 11 of temporary register) A B R5 R7 < 5 > Save V U Temporary register T < 1 > Save PSW W D H E L < 4 > RSS0 IE 0 VP UP < 3 > Select register bank (RBS0 to RBS2n) X C R4 R6 (0 to 7)
40
PD784054(A)
8.4 Macro Service
The PD784054(A) has a total of seven types of macro service. Each macro service is outlined below. (1) Counter mode: EVTCNT * Operation (a) Increments or decrements an 8-bit macro service counter (MSC). (b) A vectored interrupt request is generated when the value of MSC reaches 0.
MSC
+1 / _1
* Application example: Event counter, measurement of number of times of capture (2) Block transfer mode: BLKTRS * Operation (a) Transfers block data between the buffer and an SFR specified by the SFR pointer (SFR.PTR). (b) The transfer source and destination can be an SFR or buffer. The length of the data to be transferred can be byte or word. (c) The number of times data is to be transferred (block size) is specified by MSC. (d) MSC is auto-decremented (-1) each time the macro service has been executed. (e) When the value of MSC has reached 0, a vectored interrupt request is generated.
SFR.PTR _1 MSC
Buffer N
Buffer 1
SFR
Internal bus
* Application example: Data transfer/reception of serial interface
41
PD784054(A)
(3) Block transfer mode (with memory pointer): BLKTRS-P * Operation This is the block transfer mode in (2) with a memory pointer (MEM.PTR) appended. The appended buffer area of MEM.PTR can be freely set on the memory space. Remark MEMP is auto-incremented (+1: byte data transfer/+2: word data transfer) each time the macro service has been executed.
SFR.PTR _1 MSC
Buffer N
+1 / +2
MEM.PTR Buffer 1 SFR
Internal bus
* Application example: Same as (2) (4) Data differential mode: DTADIF * Operation (a) Calculates the difference between the contents of the SFR specified by SFR pointer (SFR.PTR) (current value) and the contents of the SFR loaded to the last data buffer (LDB). (b) Stores the result of the calculation to a predetermined buffer area. (c) Stores the contents of the current value of SFR to LDB. (d) The number of times the data is to be transferred (block size) is specified by MSC. The value of MSC is auto-decremented (-1) each time the macro service has been executed. (e) When the value of MSC has reached 0, a vectored interrupt request is generated. Remark The differential calculation can be performed only an SFR of 16-bit configuration.
SFR.PTR _1 MSC LDB Buffer N SFR
Buffer 1
Differential calculation
Internal bus
* Application example: Measurement of period and pulse width by capture register of timer 0
42
PD784054(A)
(5) Data differential mode (with memory pointer): DTADIF-P * Operation This is the data differential mode in (4) with a memory pointer (MEM.PTR) appended. The appended MEM.PTR can set a buffer area to which the differential data is to be stored on the memory space freely. Remarks 1. The differential calculation can be performed only an SFR of 16-bit configuration. 2. The buffer is specified by the result of an operation between MEM.PTR and MSCNote. The value of MEM.PTR is not updated after the data has been transferred. Note MEM.PTR - (MSC x 2) + 2
SFR.PTR Buffer N _1 MSC LDB SFR
MEM.PTR Buffer 1 Differential calculation
Internal bus
* Application example: Same as (4) (6) CPU monitoring mode0: SFLF0 * Operation (a) Checks the internal operation of the CPU. (b) When the blocks are operating normally, the value given by subtracting 10 from the initial value is transferred to the SFR specified by the SFR pointer (SFR.PTR). * Application example: Used for self checking of the CPU during normal operation. (7) CPU monitoring mode1: SELF1 * Operation (a) Checks the internal operation of the CPU. (b) When the blocks are operating normally, the value given by subtracting 8 from the initial value is transferred to the SFR specified by the SFR pointer (SFR.PTR). * Application example: Used for self checking of the CPU during normal operation.
43
PD784054(A)
9. LOCAL BUS INTERFACE
The PD784054(A) can be connected to an external memory or I/O (memory mapped I/O), supporting a 1Mbyte memory space (refer to Figure 9-1). Figure 9-1. Example of Local Bus Interface (with external 8-bit bus specified)
Address bus
PD784054(A)
A16-A19
Decoder
RD LWR SRAM PROM Character generator
AD0-AD7
Data bus
ASTB
Latch
Address bus AD8-AD15
Gate array I/O expansion Centronics I/F, etc.
44
PD784054(A)
9.1 Memory Expansion
The external program memory or data memory can be expanded from 256 bytes up to 1M bytes in seven steps. When an external device is connected, the address/data bus and read/write strobe signals are controlled by using ports 4 through 6 and P90 through P93 pins. The functions of these ports and pins are set by the memory expansion mode register (MM). Table 9-1. Setting of Pin Function
Memory Expansion Mode Register MM0-MM3 Port mode External memory expansion mode Port 4 P40-P47 General-purpose port AD0-AD7 AD8 to AD15 are set stepwise. Rest of pins can be used as general-purpose port pins. A16 through A19 are set stepwise. Rest of pins can be used as general-purpose port pins. P90 P91 P92 P93 : : : : RD LWR HWR ASTB Port 5 P50-P57 Pin Function Port 6 P60-P63 P90-P93
Remark AD8 through AD15 are used as address bus. The number of pins of ports 5 and 6 that are used as address bus pins can be changed according to the size of the external memory connected (external address space), so that the external memory can be expanded stepwise. The pins not used as address bus pins can be used as general-purpose I/O port pins (refer to Table 9-2). The external address space can be set in seven steps by MM. Table 9-2. Operations of Ports 5 and 6 (in external memory expansion mode)
Port 5 P50 P51 P52 P53 P54 P55 P56 P57 P60 Port 6 P61 P62 P63 256 bytes or less Note 1K bytes or less Note AD10 AD11 AD12 AD13 AD14 AD15 A16 A17 A18 A19 4K bytes or less Note 16K bytes or less Note 64K bytes or less 256K bytes or less 1M bytes or less External address space
General-purpose port AD8 AD9
Note
When the external 16-bit bus is specified, do not set MM such that the external address space is of this size. When the external 16-bit bus is specified, set MM such that all the pins of port 5 (P50 through P57) are used as AD pins (AD8 through AD15).
Caution
45
PD784054(A)
9.2 Memory Space
The 1M-byte memory space is divided into the following eight spaces of logical addresses. Each space can be controlled by using the programmable wait function and bus sizing function. Figure 9-2. Memory Space
F F F F FH
512K bytes
8 0 0 0 0H 7 F F F FH 256K bytes 4 0 0 0 0H 3 F F F FH 128K bytes 2 0 0 0 0H 1 F F F FH 64K bytes 1 0 0 0 0H 0 F F F FH 16K bytes 0C0 0 0H 0 B F F FH 16K bytes 0 8 0 0 0H 0 7 F F FH 16K bytes 0 4 0 0 0H 0 3 F F FH 16K bytes 0 0 0 0 0H
9.3 Programmable Wait
A wait state can be inserted to each of the eight memory spaces while the RD, LWR, and HWR signals are active. Even if memories with different access times are connected, therefore, the overall efficiency of the system is not degraded. In addition, an address wait function that extends the active period of the ASTB signal is also available to extend the address decode time (this function can be set to all the spaces).
9.4 Bus Sizing Function
The PD784054(A) can change the external data bus width between 8 and 16 bits when an external device is connected. Even if the memory space is divided by eight, the bus width of each memory space can be specified independently.
46
PD784054(A)
10. STANDBY FUNCTION
The PD784054(A) has the following standby function modes that reduce the power consumption of the chip. * HALT mode : This mode stops the operating clock of the CPU. It can reduce the average power consumption through intermittent operation by combination of a normal operation and this mode. * IDLE mode : This mode stops the entire system with the operation of the oscillation circuit continuing. Normal program operation can be restored from this mode with the power consumption close to that in the STOP mode and time equivalent to that in the HALT mode. * STOP mode : This mode stops the oscillator and stops all the internal operations of the chip to minimize the power consumption to the level of only leakage current. * Standby function invalid mode : This mode makes the standby function (HALT/IDLE/STOP modes) invalid by asserting the MODE1 pin high. This mode is useful when the standby mode must not be used because of the application. These modes are programmable. Macro service can be started from the HALT mode. Figure 10-1. Standby Status Transition
MODE1=H Standby function invalid
MOD
MODE1=L
E1=
H
Waits for stabilization of oscillation
ilizatio on stab Oscillati expires time
n
Program operation
L E1= MOD Macro service request
End of first processing End of macro service Macro service
ID RE LE SE set T tin NM inp g ut I
ing ett P s put O ST ET in S RE
STOP (standby)
IDLE (standby)
Interrupt request of masked interrupt
HALT (standby)
Note
Only unmasked interrupt request
Remark Only external input of NMI is valid. The watchdog timer cannot be used to release the standby mode (STOP/HALT/IDLE).
Ma En cro d o se f fi rvic e rst pr req u oc es est sin g
t es qu ut re pt inp g rru ET ttin te S se In RE LT HA
NM
I
t No e
47
PD784054(A)
11. RESET FUNCTION
When a low level is input to the RESET pin, the internal hardware is initialized (reset status). When the RESET signal goes high, the following data is set to the program counter (PC). * Low-order 8 bits of PC : * Middle 8 bits of PC : * High-order 4 bits of PC: contents of address 0000H contents of address 0001H 0
Program execution is started from the set contents of the PC. Therefore, the contents of the PC are assumed as a branch destination address, and the program can be reset and started from any address. Set the contents of each register by program as necessary. To prevent malfunctioning due to noise, a noise rejection circuit is provided to the RESET input circuit. This noise rejection circuit is a sampling circuit with analog delay. Figure 11-1. Accepting Reset
Delay
Delay
Delay
PC initialization
Instruction execution at reset start address
RESET (input)
Internal reset signal
Reset starts
Reset ends
Keep the RESET signal active until the oscillation stabilization time (about 40 ms) elapses when executing a reset operation on power application or when releasing the STOP mode by reset. Figure 11-2. Reset Operation on Power Application
Oscillation stabilization time
Delay
Initializes PC
Instruction execution at reset start address
VDD
RESET (input)
Internal reset signal
Reset ends
48
PD784054(A)
12. INSTRUCTION SET
(1) 8-bit instructions (( ): combination realized by writing A as r) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA Table 12-1. Instructions for 8-Bit Addressing
2nd Operand #byte A r r' 1st Operand A (MOV) (MOV) MOV XCH (MOV)Note 6 (XCH)Note 6 MOV (XCH) (MOV) (XCH) ADDNote 1 (XCH) saddr saddr' sfr !addr16 !!addr24 mem [saddrp] [%saddrg] MOV XCH ADDNote 1 r3 PSWL PSWH MOV (MOV) (XCH) (ADD)Note 1 RORNote 3 MULU DIVUW INC DEC saddr MOV (MOV)Note 6 MOV MOV XCH ADDNote 1 sfr MOV MOV MOV ADDNote 1 (ADD)Note 1 ADDNote 1 INC DEC DBNZ PUSH POP CHKL CHKLA !addr16 !!addr24 mem [saddrp] [%saddrg] mem3 ROR4 ROL4 r3 PSWL PSWH B, C STBC, WDM [TDE+] [TDE-] MOV (MOV) (ADD)Note 1 MOVMNote 4 MOVBKNote 5 DBNZ MOV MOV MOV (MOV) ADDNote 1 MOV ADDNote 1 MOV ADDNote 1 (ADD)Note 1 ADDNote 1 [WHL+] [WHL-] n None Note 2
(ADD)Note 1 (ADD)Note 1 (ADD)Note 1, 6 (ADD)Note 1 ADDNote 1 r MOV (MOV) MOV XCH MOV XCH ADDNote 1 MOV XCH ADDNote 1 MOV XCH ADDNote 1 (XCH)
(ADD)Note 1 ADDNote 1
Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD. 2. Either the second operand is not used, or the second operand is not an operand address. 3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR. 4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM. 5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK. 6. If saddr is saddr2 in this combination, some instructions have a short code length.
49
PD784054(A)
(2) 16-bit instructions (( ): combination realized by writing AX as rp) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 12-2. Instructions for 16-Bit Addressing
2nd Operand #word AX rp rp' 1st Operand AX (MOVW) ADDW
Note 1
saddrp saddrp' (MOVW)Note 3 (XCHW)Note 3
sfrp
!addr16 !!addr24
mem [saddrp] [%saddrg]
[WHL+]
byte
n
NoneNote 2
(MOVW) (XCHW)
(MOVW) (XCHW)
MOVW (XCHW)
(MOVW) XCHW
MOVW XCHW
(MOVW) (XCHW) MULWNote 4 INCW DECW INCW DECW
(ADDW)Note 1 (ADDW)Note 1 (ADDW)Note 1, 3 (ADDW)Note 1 rp MOVW ADDW
Note 1
(MOVW) (XCHW)
MOVW XCHW
MOVW XCHW ADDWNote 1 MOVW XCHW ADDWNote 1
MOVW XCHW ADDWNote 1
MOVW
SHRW SHLW
(ADDW)Note 1 ADDWNote 1 saddrp MOVW ADDW
Note 1
(MOVW)Note 3 MOVW (ADDW)Note 1 ADDWNote 1
sfrp
MOVW
MOVW
MOVW
PUSH POP MOVTBLW
ADDWNote 1 (ADDW)Note 1 ADDWNote 1 !addr16 !!addr24 mem [saddrp] [%saddrg] PSW SP ADDWG SUBWG post MOVW MOVW (MOVW) MOVW
PUSH POP
PUSH POP PUSHU POPU
[TDE+] byte
(MOVW)
SACW MACW MACSW
Notes 1. SUBW and CMPW are the same as ADDW. 2. Either the second operand is not used, or the second operand is not an operand address. 3. If saddrp is saddrp2 in this combination, some instructions have a short code length. 4. MULUW and DIVUX are the same as MULW.
50
PD784054(A)
(3) 24-bit instructions (( ): combination realized by writing WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 12-3. Instructions for 24-Bit Addressing
2nd Operand 1st Operand WHL (MOVG) (ADDG) (SUBG) rg MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) #imm24 WHL rg rg' (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) ADDG SUBG MOVG MOVG INCG DECG PUSH POP saddrg !!addr24 mem1 [%saddrg] SP MOVG (MOVG) (MOVG) MOVG MOVG MOVG INCG DECG MOVG MOVG (MOVG) MOVG MOVG MOVG saddrg !!addr24 mem1 [%saddrg] SP NoneNote
Note
Either the second operand is not used, or the second operand is not an operand address.
51
PD784054(A)
(4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BCLR, BFSET Table 12-4. Addressing of Bit Manipulation Instructions
2nd Operand CY saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit 1st Operand CY !!addr24.bit MOV1 AND1 OR1 XOR1 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit MOV1 NOT1 SET1 CLR1 BF BT BTCLR BFSET /saddr.bit /sfr.bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit AND1 OR1 NOT1 SET1 CLR1 NoneNote
Note
Either the second operand is not used, or the second operand is not an operand address.
52
PD784054(A)
(5) Call/return/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 12-5. Addressing for Call/Return/Branch Instructions
Operand of instruction address Basic instruction BCNote BR CALL BR CALL BR RETCS RETCSB Compound instruction BF BT BTCLR BFSET DBNZ CALL BR CALL BR CALL BR CALL BR CALL BR CALLF CALLT BRKCS BRK RET RETI RETB $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None
Note
BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC.
(6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS
53
PD784054(A)
13. ELECTRICAL SPECIFICATIONS
(1) Electrical specifications of PD784054(A) (1/6) Absolute Maximum Ratings (TA = 25 C)
Parameter Supply voltage Symbol VDD AVDD AVSS Input voltage Output voltage Low-level output current VI VO IOL All output pins Total of all output pins High-level output current IOH All output pins Total of all output pins Analog input voltage VIAN Note 2 AVDD > VDD VDD AVDD A/D converter reference input voltage Operating temperature Storage temperature TA Tstg AVREF AVDD > VDD VDD AVDD Note 1 Conditions Ratings -0.5 to +7.0 -0.5 to VDD + 0.5 -0.5 to +0.5 -0.5 to VDD + 0.5 7.0 -0.5 to VDD + 0.5 15 150 -10 -100 -0.5 to VDD + 0.5 -0.5 to AVDD + 0.5 -0.5 to VDD + 0.5 -0.5 to AVDD + 0.5 -40 to +85 -65 to +150 C C V Unit V V V V V mA mA mA mA V
Notes 1. Pins other than the pins in Note 2. 2. Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings. Recommended Operating Conditions
Oscillation Frequency 8 MHz fXX 25 MHz TA -40 to +85 C VDD 4.5 to 5.5 V
Capacitance (TA = 25 C, VSS = VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO f = 1 MHz 0 V except measured pins Conditions MIN. TYP. MAX. 10 10 10 Unit pF pF pF
54
PD784054(A)
(1) Electrical specifications of PD784054(A) (2/6) Oscillation Circuit Characteristics (TA = -40 to +85 C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Resonator Ceramic resonator or crystal resonator
VSS X1 X2
Recommended Circuit
Item Oscillation frequency (fXX)
MIN. 8
MAX. 25
Unit MHz
C1
C2
External clock
X1 input frequency (fX)
8
25
MHz
X1
X2 OpenNote HCMOS inverter
X1 input rise, fall time
0
5
ns
X1 input high-, low-level width
20
105
ns
Note
When the EXTC bit of the oscillation stabilization time specification register (OSTS) = 0. Input the reverse phase clock of the pin X1 to the pin X2 when the EXTC bit = 1.
Caution
When using a system clock oscillation circuit, wire the portion enclosed by the dotted line in the diagram above as follows to prevent adverse influence from wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with any other signal lines. Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground potential for the capacitor in the oscillation circuit at the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not extract any signal from the oscillation circuit.
55
PD784054(A)
(1) Electrical specifications of PD784054(A) (3/6) DC Characteristics (TA = -40 to +85C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter Low-level input voltage High-level input voltage Symbol VIL VIH1 VIH2 Low-level output voltage High-level output voltage Input leakage current Analog pin input leakage current Output leakage current VDD supply current VOL VOH ILI ILIAN ILO IDD1 IDD2 IDD3 Data retention voltage Data retention current VDDDR IDDDR Note 1 Note 2 IOL = 2.0 mA IOH = -400 A Note 3 Note 4 0 V VO VDD Operating mode (fXX = 25 MHz) HALT mode (fXX = 25 MHz) IDLE mode (fXX = 25 MHz) STOP mode STOP mode VDDDR = 2.5 V VDDDR = 5 V 10 % Pull-up resistor RL 15 2.5 2 15 40 15 50 80 40 25 10 0 V VI VDD 0 V VI AVDD VDD - 1.0 10 1 10 70 50 20 Conditions MIN. 0 2.2 0.8 VDD TYP. MAX. 0.8 VDD VDD 0.45 V V Unit V V
A A A
mA mA mA V
A A
k
Notes 1. Pins other than pins in Note 2 2. P20/NMI, P21/INTP0/TO00, P22/INTP1/TO01, P23/INTP2/TO02, P24/INTP3/TO03, P25/INTP4, P26/ INTP5, P27/INTP6, P34/ASCK/SCK1, P37/ASCK2/SCK2, X1, X2, RESET 3. Input and I/O pins (except X1 and X2, and P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 used as analog inputs) 4. Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 (pins used as analog input, only during the nonsampling operation)
56
PD784054(A)
(1) Electrical specifications of PD784054(A) (4/6) AC Characteristics (TA = -40 to +85 C, VDD = 4.5 to 5.5 V, VSS = 0 V) Read/write operation
Parameter System clock cycle time Address setup time (vs. ASTB) Address hold time (vs. ASTB) ASTB high-level width AddressRD delay time RDaddress float time Addressdata input time RDdata input time ASTBRD delay time Data hold time (vs. RD) RDaddress active time RD low-level width AddressLWR, HWR delay time LWR, HWRdata output time ASTBLWR, HWR delay time Data setup time (vs. LWR, HWR) Data hold time (vs. LWR, HWR) LWR, HWR ASTB delay time LWR, HWR low-level width AddressWAIT input time ASTBWAIT input time ASTBWAIT hold time ASTBWAIT delay time RDWAIT input time RDWAIT hold time RDWAIT delay time LWR, HWRWAIT input time LWR, HWRWAIT hold time LWR, HWRWAIT delay time Symbol tCYK tSAST tHSTA tWSTH tDAR tFRA tDAID tDRID tDSTR tHRID tDRA tWRL tDAW tDWOD tDSTW tSODW tHWOD tDWST tWWL tDAWT tDSTWT tHSTWT tDSTWTH tDRWT tHRWT tDRWTH tDWWT tHWWT tDWWTH 0.5T - 16 (1.5 + n) T - 25 0.5T - 14 1.5T - 15 (1.5 + n) T - 36 (2 + a) T - 50 1.5T - 40 (1.5 + n) T + 5 (1.5 + n) T - 40 T - 40 (1 + n) T + 5 (1 + n) T - 40 T - 40 (1 + n) T + 5 (1 + n) T - 40 85 120 Note 85 120 Note 40 125 160 Note 40 24 95 26 105 84 110 80 0.5T - 14 (1.5 + n) T - 30 (1 + a) T - 15 (2.5 + a + n) T - 56 (1.5 + n) T - 48 0.5T - 16 24 0 26 90 65 15 (0.5 + a) T - 20 0.5T - 20 (0.5 + a) T - 17 (1 + a) T - 15 Expression MIN. 80 20 20 23 65 0 144 72 MAX. 250 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
Specification when an external wait is inserted
Remarks 1. T = tCYK = 1/fCLK (fCLK is internal system clock frequency) 2. a = 1 when an address wait is inserted, otherwise, 0. 3. n indicates the number of the wait cycles by specifying the external wait pins (WAIT) or programmable wait control registers 1, 2 (PWC1, PWC2). (n 0. n 1 for tDSTWTH, tDRWTH, tDWWTH). 4. Calculate values in the expression column with the system clock cycle time to be used because these values depend on the system clock cycle time (tCYK = T). The values in the above expression column are calculated based on T = 80 ns.
57
PD784054(A)
(1) Electrical specifications of PD784054(A) (5/6) Serial Operation (TA = -40 to +85 C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter Serial clock cycle time Symbol tCYSK Conditions SCK1, SCK2 output BRG SCK1, SCK2 input Serial clock low-level width tWSKL External clock MIN. TSFT 640 0.5TSFT-40 280 0.5TSFT-40 280 80 80 R = 1 k, C = 100 pF 0 150 MAX. Unit ns ns ns ns ns ns ns ns ns
SCK1, SCK2 output BRG SCK1, SCK2 input External clock
Serial clock high-level width
tWSKH
SCK1, SCK2 output BRG SCK1, SCK2 input External clock
SI1, SI2 setup time (vs. SCK1, SCK2) SI1, SI2 hold time (vs. SCK1, SCK2) SCK1, SCK2SO1, SO2 output delay time
tSSSK tHSSK tDSBSK
Remarks 1. TSFT is a value set in software. The minimum value is tCYK x 8. 2. tCYK = 1/fCLK (fCLK is internal system clock frequency) Other Operations (TA = -40 to +85 C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter NMI high, low-level width INTP0-INTP6 high, low-level width RESET high, low-level width Symbol tWNIH, tWNIL tWITH, tWITL tWRSH, tWRSL Conditions MIN. 10 4 10 MAX. Unit
s
tCYSMP
s
Remarks 1. tCYSMP is a sampling clock set in the noise protection control register (NPC) in software. When NIn = 0, tCYSMP = tCYK When NIn = 1, tCYSMP = tCYK x 4 2. tCYK = 1/fCLK (fCLK is internal system clock frequency) 3. NIn: Bit n of NPC (n = 0-6) AC Timing Test Point
VDD 0.8 VDD or 2.2 V 0.8 V 0V Test point 0.8 VDD or 2.2 V 0.8 V
58
PD784054(A)
(1) Electrical specifications of PD784054(A) (6/6) AD Converter Characteristics (TA = -40 to +85 C, VDD = 4.5 to 5.5 V, VSS = AVSS = 0 V, VDD - 0.5 V AVDD VDD)
Parameter Resolution Total error Note 4.5 V AVREF AVDD 3.4 V AVREF < 4.5 V Quantization error Conversion time Sampling time Zero-scale error Note tCONV tSAMP 80 ns tCYK 250 ns 80 ns tCYK 250 ns 4.5 V AVREF AVDD 3.4 V AVREF < 4.5 V Full-scale error Note 4.5 V AVREF AVDD 3.4 V AVREF < 4.5 V Nonlinearity errorNote 4.5 V AVREF AVDD 3.4 V AVREF < 4.5 V Analog input voltage A/D converter reference input voltage AVREF current AVDD supply current A/D converter data retention current VIAN AVREF AIREF AIDD AIDDDR STOP mode AVDDDR = 2.5 V AVDDDR = 5 V 10% -0.3 3.4 1.0 2.0 2 10 169 20 1.5 1.5 1.5 1.5 1.5 1.5 3.5 4.5 3.5 4.5 2.5 4.5 AVREF+0.3 AVDD 3.0 6.0 10 50 Symbol Conditions MIN. 10 0.5 0.7 1/2 TYP. MAX. Unit bit %FSR %FSR LSB tCYK tCYK LSB LSB LSB LSB LSB LSB V V mA mA
A A
Note
The quantization error is excluded.
Remark tCYK = 1/fCLK (fCLK is internal system clock frequency).
59
PD784054(A)
(2) Electrical specifications of PD784054(A1) (1/6) Absolute Maximum Ratings (TA = 25 C)
Parameter Supply voltage Symbol VDD AVDD AVSS Input voltage Output voltage Low-level output current VI VO IOL All output pins Total of all output pins High-level output current IOH All output pins Total of all output pins Analog input voltage VIAN Note 2 AVDD > VDD VDD AVDD A/D converter reference input voltage Operating temperature Storage temperature TA Tstg AVREF AVDD > VDD VDD AVDD Note 1 Conditions Ratings -0.5 to +7.0 -0.5 to VDD + 0.5 -0.5 to +0.5 -0.5 to VDD + 0.5 7.0 -0.5 to VDD + 0.5 15 150 -10 -100 -0.5 to VDD + 0.5 -0.5 to AVDD + 0.5 -0.5 to VDD + 0.5 -0.5 to AVDD + 0.5 -40 to +110 -65 to +150 C C V Unit V V V V V mA mA mA mA V
Notes 1. Pins other than the pins in Note 2. 2. Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings. Recommended Operating Conditions
Oscillation Frequency 8 MHz fXX 20 MHz TA -40 to +110 C VDD 4.5 to 5.5 V
Capacitance (TA = 25 C, VSS = VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO f = 1 MHz 0 V except measured pins Conditions MIN. TYP. MAX. 10 10 10 Unit pF pF pF
60
PD784054(A)
(2) Electrical specifications of PD784054(A1) (2/6) Oscillation Circuit Characteristics (TA = -40 to +110 C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Resonator Ceramic resonator or crystal resonator Recommended Circuit Item Oscillation frequency (fXX) MIN. 8 MAX. 20 Unit MHz
VSS
X1
X2
C1
C2
External clock
X1 input frequency (fX)
8
20
MHz
X1
X2 OpenNote HCMOS inverter
X1 input rise, fall time
0
5
ns
X1 input high-, low-level width
20
105
ns
Note
When the EXTC bit of the oscillation stabilization time specification register (OSTS) = 0. Input the reverse phase clock of the pin X1 to the pin X2 when the EXTC bit = 1.
Caution
When using a system clock oscillation circuit, wire the portion enclosed by the dotted line in the diagram above as follows to prevent adverse influence from wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with any other signal lines. Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground potential for the capacitor in the oscillation circuit at the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not extract any signal from the oscillation circuit.
61
PD784054(A)
(2) Electrical specifications of PD784054(A1) (3/6) DC Characteristics (TA = -40 to +110C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter Low-level input voltage High-level input voltage Symbol VIL VIH1 VIH2 Low-level output voltage High-level output voltage Input leakage current Analog pin input leakage current Output leakage current VDD supply current VOL VOH ILI ILIAN ILO IDD1 IDD2 IDD3 Data retention voltage Data retention current VDDDR IDDDR Note 1 Note 2 IOL = 2.0 mA IOH = -400 A Note 3 Note 4 0 V VO VDD Operating mode (fXX = 20 MHz) HALT mode (fXX = 20 MHz) IDLE mode (fXX = 20 MHz) STOP mode STOP mode VDDDR = 2.5 V VDDDR = 5 V 10 % Pull-up resistor RL 15 2.5 2 15 40 100 1000 80 30 15 10 0 V VI VDD 0 V VI AVDD VDD - 1.0 10 2 10 60 30 20 Conditions MIN. 0 2.2 0.8 VDD TYP. MAX. 0.8 VDD VDD 0.45 V V Unit V V
A A A
mA mA mA V
A A
k
Notes 1. Pins other than pins in Note 2 2. P20/NMI, P21/INTP0/TO00, P22/INTP1/TO01, P23/INTP2/TO02, P24/INTP3/TO03, P25/INTP4, P26/ INTP5, P27/INTP6, P34/ASCK/SCK1, P37/ASCK2/SCK2, X1, X2, RESET 3. Input and I/O pins (except X1 and X2, and P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 used as analog inputs) 4. Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 (pins used as analog input, only during the nonsampling operation)
62
PD784054(A)
(2) Electrical specifications of PD784054(A1) (4/6) AC Characteristics (TA = -40 to +110 C, VDD = 4.5 to 5.5 V, VSS = 0 V) Read/write operation
Parameter System clock cycle time Address setup time (vs. ASTB) Address hold time (vs. ASTB) ASTB high-level width AddressRD delay time RDaddress float time Addressdata input time RDdata input time ASTBRD delay time Data hold time (vs. RD) RDaddress active time RD low-level width AddressLWR, HWR delay time LWR, HWRdata output time ASTBLWR, HWR delay time Data setup time (vs. LWR, HWR) Data hold time (vs. LWR, HWR) LWR, HWR ASTB delay time LWR, HWR low-level width AddressWAIT input time ASTBWAIT input time ASTBWAIT hold time ASTBWAIT delay time RDWAIT input time RDWAIT hold time RDWAIT delay time LWR, HWRWAIT input time LWR, HWRWAIT hold time LWR, HWRWAIT delay time Symbol tCYK tSAST tHSTA tWSTH tDAR tFRA tDAID tDRID tDSTR tHRID tDRA tWRL tDAW tDWOD tDSTW tSODW tHWOD tDWST tWWL tDAWT tDSTWT tHSTWT tDSTWTH tDRWT tHRWT tDRWTH tDWWT tHWWT tDWWTH 0.5T - 16 (1.5 + n) T - 25 0.5T - 14 1.5T - 15 (1.5 + n) T - 36 (2 + a) T - 50 1.5T - 40 (1.5 + n) T + 5 (1.5 + n) T - 40 T - 40 (1 + n) T + 5 (1 + n) T - 40 T - 40 (1 + n) T + 5 (1 + n) T - 40 105 160 Note 105 160 Note 60 155 210 Note 60 34 125 36 135 114 150 110 0.5T - 14 (1.5 + n) T - 30 (1 + a) T - 15 (2.5 + a + n) T - 56 (1.5 + n) T - 53 0.5T - 16 34 0 36 120 85 15 (0.5 + a) T - 20 0.5T - 20 (0.5 + a) T - 17 (1 + a) T - 15 Expression MIN. 100 30 30 33 85 0 194 97 MAX. 250 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
Specification when an external wait is inserted
Remarks 1. T = tCYK = 1/fCLK (fCLK is internal system clock frequency) 2. a = 1 when an address wait is inserted, otherwise, 0. 3. n indicates the number of the wait cycles by specifying the external wait pins (WAIT) or programmable wait control registers 1, 2 (PWC1, PWC2). (n 0. n 1 for tDSTWTH, tDRWTH, tDWWTH). 4. Calculate values in the expression column with the system clock cycle time to be used because these values depend on the system clock cycle time (tCYK = T). The values in the above expression column are calculated based on T = 100 ns.
63
PD784054(A)
(2) Electrical specifications of PD784054(A1) (5/6) Serial Operation (TA = -40 to +110 C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter Serial clock cycle time Symbol tCYSK Conditions SCK1, SCK2 output BRG SCK1, SCK2 input Serial clock low-level width tWSKL External clock MIN. TSFT 800 0.5TSFT-40 360 0.5TSFT-40 360 80 80 R = 1 k, C = 100 pF 0 150 MAX. Unit ns ns ns ns ns ns ns ns ns
SCK1, SCK2 output BRG SCK1, SCK2 input External clock
Serial clock high-level width
tWSKH
SCK1, SCK2 output BRG SCK1, SCK2 input External clock
SI1, SI2 setup time (vs. SCK1, SCK2) SI1, SI2 hold time (vs. SCK1, SCK2) SCK1, SCK2SO1, SO2 output delay time
tSSSK tHSSK tDSBSK
Remarks 1. TSFT is a value set in software. The minimum value is tCYK x 8. 2. tCYK = 1/fCLK (fCLK is internal system clock frequency) Other Operations (TA = -40 to +110 C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter NMI high, low-level width INTP0-INTP6 high, low-level width RESET high, low-level width Symbol tWNIH, tWNIL tWITH, tWITL tWRSH, tWRSL Conditions MIN. 10 4 10 MAX. Unit
s
tCYSMP
s
Remarks 1. tCYSMP is a sampling clock set in the noise protection control register (NPC) in software. When NIn = 0, tCYSMP = tCYK When NIn = 1, tCYSMP = tCYK x 4 2. tCYK = 1/fCLK (fCLK is internal system clock frequency) 3. NIn: Bit n of NPC (n = 0-6) AC Timing Test Point
VDD 0.8 VDD or 2.2 V 0.8 V 0V Test point 0.8 VDD or 2.2 V 0.8 V
64
PD784054(A)
(2) Electrical specifications of PD784054(A1) (6/6) AD Converter Characteristics (TA = -40 to +110 C, VDD = 4.5 to 5.5 V, VSS = AVSS = 0 V, VDD - 0.5 V AVDD VDD)
Parameter Resolution Total error Note 4.5 V AVREF AVDD 3.4 V AVREF < 4.5 V Quantization error Conversion time Sampling time Zero-scale error Note tCONV tSAMP 4.5 V AVREF AVDD 3.4 V AVREF < 4.5 V Full-scale errorNote 4.5 V AVREF AVDD 3.4 V AVREF < 4.5 V Nonlinearity errorNote 4.5 V AVREF AVDD 3.4 V AVREF < 4.5 V Analog input voltage A/D converter reference input voltage AVREF current AVDD supply current A/D converter data retention current VIAN AVREF AIREF AIDD AIDDDR STOP mode AVDDDR = 2.5 V AVDDDR = 5 V 10% -0.3 3.4 3.0 2.0 2 10 169 20 1.5 1.5 1.5 1.5 1.5 1.5 3.5 4.5 3.5 4.5 2.5 4.5 AVREF+0.3 AVDD 4.0 6.0 100 1000 Symbol Conditions MIN. 10 0.5 0.7 1/2 TYP. MAX. Unit bit %FSR %FSR LSB tCYK tCYK LSB LSB LSB LSB LSB LSB V V mA mA
A A
Note
The quantization error is excluded.
Remark tCYK = 1/fCLK (fCLK is internal system clock frequency).
65
PD784054(A)
(3) Electrical specifications of PD784054(A2) (1/6) Absolute Maximum Ratings (TA = 25 C)
Parameter Supply voltage Symbol VDD AVDD AVSS Input voltage Output voltage Low-level output current VI VO IOL All output pins Total of all output pins High-level output current IOH All output pins Total of all output pins Analog input voltage VIAN Note 2 AVDD > VDD VDD AVDD A/D converter reference input voltage Operating temperature Storage temperature TA Tstg AVREF AVDD > VDD VDD AVDD Note 1 Conditions Ratings -0.5 to +7.0 -0.5 to VDD + 0.5 -0.5 to +0.5 -0.5 to VDD + 0.5 7.0 -0.5 to VDD + 0.5 15 150 -10 -100 -0.5 to VDD + 0.5 -0.5 to AVDD + 0.5 -0.5 to VDD + 0.5 -0.5 to AVDD + 0.5 -40 to +125 -65 to +150 C C V Unit V V V V V mA mA mA mA V
Notes 1. Pins other than the pins in Note 2. 2. Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings. Recommended Operating Conditions
Oscillation Frequency 8 MHz fXX 20 MHz TA -40 to +125 C VDD 4.5 to 5.5 V
Capacitance (TA = 25 C, VSS = VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO f = 1 MHz 0 V except measured pins Conditions MIN. TYP. MAX. 10 10 10 Unit pF pF pF
66
PD784054(A)
(3) Electrical specifications of PD784054(A2) (2/6) Oscillation Circuit Characteristics (TA = -40 to +125 C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Resonator Ceramic resonator or crystal resonator Recommended Circuit Item Oscillation frequency (fXX) MIN. 8 MAX. 20 Unit MHz
VSS
X1
X2
C1
C2
External clock
X1 input frequency (fX)
8
20
MHz
X1
X2 OpenNote HCMOS inverter
X1 input rise, fall time
0
5
ns
X1 input high-, low-level width
20
105
ns
Note
When the EXTC bit of the oscillation stabilization time specification register (OSTS) = 0. Input the reverse phase clock of the pin X1 to the pin X2 when the EXTC bit = 1.
Caution
When using a system clock oscillation circuit, wire the portion enclosed by the dotted line in the diagram above as follows to prevent adverse influence from wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with any other signal lines. Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground potential for the capacitor in the oscillation circuit at the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not extract any signal from the oscillation circuit.
67
PD784054(A)
(3) Electrical specifications of PD784054(A2) (3/6) DC Characteristics (TA = -40 to +125C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter Low-level input voltage High-level input voltage Symbol VIL VIH1 VIH2 Low-level output voltage High-level output voltage Input leakage current Analog pin input leakage current Output leakage current VDD supply current VOL VOH ILI ILIAN ILO IDD1 IDD2 IDD3 Data retention voltage Data retention current VDDDR IDDDR Note 1 Note 2 IOL = 2.0 mA IOH = -400 A Note 3 Note 4 0 V VO VDD Operating mode (fXX = 20 MHz) HALT mode (fXX = 20 MHz) IDLE mode (fXX = 20 MHz) STOP mode STOP mode VDDDR = 2.5 V VDDDR = 5 V 10 % Pull-up resistor RL 15 2.5 2 15 40 100 1000 80 30 15 10 0 V VI VDD 0 V VI AVDD VDD - 1.0 10 2 10 60 30 20 Conditions MIN. 0 2.2 0.8 VDD TYP. MAX. 0.8 VDD VDD 0.45 V V Unit V V
A A A
mA mA mA V
A A
k
Notes 1. Pins other than pins in Note 2 2. P20/NMI, P21/INTP0/TO00, P22/INTP1/TO01, P23/INTP2/TO02, P24/INTP3/TO03, P25/INTP4, P26/ INTP5, P27/INTP6, P34/ASCK/SCK1, P37/ASCK2/SCK2, X1, X2, RESET 3. Input and I/O pins (except X1 and X2, and P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 used as analog inputs) 4. Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 (pins used as analog input, only during the nonsampling operation)
68
PD784054(A)
(3) Electrical specifications of PD784054(A2) (4/6) AC Characteristics (TA = -40 to +125 C, VDD = 4.5 to 5.5 V, VSS = 0 V) Read/write operation
Parameter System clock cycle time Address setup time (vs. ASTB) Address hold time (vs. ASTB) ASTB high-level width AddressRD delay time RDaddress float time Addressdata input time RDdata input time ASTBRD delay time Data hold time (vs. RD) RDaddress active time RD low-level width AddressLWR, HWR delay time LWR, HWRdata output time ASTBLWR, HWR delay time Data setup time (vs. LWR, HWR) Data hold time (vs. LWR, HWR) LWR, HWR ASTB delay time LWR, HWR low-level width AddressWAIT input time ASTBWAIT input time ASTBWAIT hold time ASTBWAIT delay time RDWAIT input time RDWAIT hold time RDWAIT delay time LWR, HWRWAIT input time LWR, HWRWAIT hold time LWR, HWRWAIT delay time Symbol tCYK tSAST tHSTA tWSTH tDAR tFRA tDAID tDRID tDSTR tHRID tDRA tWRL tDAW tDWOD tDSTW tSODW tHWOD tDWST tWWL tDAWT tDSTWT tHSTWT tDSTWTH tDRWT tHRWT tDRWTH tDWWT tHWWT tDWWTH 0.5T - 16 (1.5 + n) T - 25 0.5T - 14 1.5T - 15 (1.5 + n) T - 36 (2 + a) T - 50 1.5T - 40 (1.5 + n) T + 5 (1.5 + n) T - 40 T - 40 (1 + n) T + 5 (1 + n) T - 40 T - 40 (1 + n) T + 5 (1 + n) T - 40 105 160 Note 105 160 Note 60 155 210 Note 60 34 125 36 135 114 150 110 0.5T - 14 (1.5 + n) T - 30 (1 + a) T - 15 (2.5 + a + n) T - 56 (1.5 + n) T - 53 0.5T - 16 34 0 36 120 85 15 (0.5 + a) T - 20 0.5T - 20 (0.5 + a) T - 17 (1 + a) T - 15 Expression MIN. 100 30 30 33 85 0 194 97 MAX. 250 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
Specification when an external wait is inserted
Remarks 1. T = tCYK = 1/fCLK (fCLK is internal system clock frequency) 2. a = 1 when an address wait is inserted, otherwise, 0. 3. n indicates the number of the wait cycles by specifying the external wait pins (WAIT) or programmable wait control registers 1, 2 (PWC1, PWC2). (n 0. n 1 for tDSTWTH, tDRWTH, tDWWTH). 4. Calculate values in the expression column with the system clock cycle time to be used because these values depend on the system clock cycle time (tCYK = T). The values in the above expression column are calculated based on T = 100 ns.
69
PD784054(A)
(3) Electrical specifications of PD784054(A2) (5/6) Serial Operation (TA = -40 to +125 C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter Serial clock cycle time Symbol tCYSK Conditions SCK1, SCK2 output BRG SCK1, SCK2 input Serial clock low-level width tWSKL External clock MIN. TSFT 800 0.5TSFT-40 360 0.5TSFT-40 360 80 80 R = 1 k, C = 100 pF 0 150 MAX. Unit ns ns ns ns ns ns ns ns ns
SCK1, SCK2 output BRG SCK1, SCK2 input External clock
Serial clock high-level width
tWSKH
SCK1, SCK2 output BRG SCK1, SCK2 input External clock
SI1, SI2 setup time (vs. SCK1, SCK2) SI1, SI2 hold time (vs. SCK1, SCK2) SCK1, SCK2SO1, SO2 output delay time
tSSSK tHSSK tDSBSK
Remarks 1. TSFT is a value set in software. The minimum value is tCYK x 8. 2. tCYK = 1/fCLK (fCLK is internal system clock frequency) Other Operations (TA = -40 to +125 C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter NMI high, low-level width INTP0-INTP6 high, low-level width RESET high, low-level width Symbol tWNIH, tWNIL tWITH, tWITL tWRSH, tWRSL Conditions MIN. 10 4 10 MAX. Unit
s
tCYSMP
s
Remarks 1. tCYSMP is a sampling clock set in the noise protection control register (NPC) in software. When NIn = 0, tCYSMP = tCYK When NIn = 1, tCYSMP = tCYK x 4 2. tCYK = 1/fCLK (fCLK is internal system clock frequency) 3. NIn: Bit n of NPC (n = 0-6) AC Timing Test Point
VDD 0.8 VDD or 2.2 V 0.8 V 0V Test point 0.8 VDD or 2.2 V 0.8 V
70
PD784054(A)
(3) Electrical specifications of PD784054(A2) (6/6) AD Converter Characteristics (TA = -40 to +125 C, VDD = 4.5 to 5.5 V, VSS = AVSS = 0 V, VDD - 0.5 V AVDD VDD)
Parameter Resolution Total error Note 4.5 V AVREF AVDD 3.4 V AVREF < 4.5 V Quantization error Conversion time Sampling time Zero-scale error Note tCONV tSAMP 4.5 V AVREF AVDD 3.4 V AVREF < 4.5 V Full-scale errorNote 4.5 V AVREF AVDD 3.4 V AVREF < 4.5 V Nonlinearity errorNote 4.5 V AVREF AVDD 3.4 V AVREF < 4.5 V Analog input voltage A/D converter reference input voltage AVREF current AVDD supply current A/D converter data retention current VIAN AVREF AIREF AIDD AIDDDR STOP mode AVDDDR = 2.5 V AVDDDR = 5 V 10% -0.3 3.4 3.0 2.0 2 10 169 20 1.5 1.5 1.5 1.5 1.5 1.5 3.5 4.5 3.5 4.5 2.5 4.5 AVREF+0.3 AVDD 4.0 6.0 100 1000 Symbol Conditions MIN. 10 0.5 0.7 1/2 TYP. MAX. Unit bit %FSR %FSR LSB tCYK tCYK LSB LSB LSB LSB LSB LSB V V mA mA
A A
Note
The quantization error is excluded.
Remark tCYK = 1/fCLK (fCLK is internal system clock frequency).
71
PD784054(A)
Read Operation (8 bits)
tCYK (CLK)
AD8-AD15 (Output) tSAST AD0-AD7 (Input/output) Hi-Z tDAID
High-order address
High-order address
Low-order address (output) tWSTH
Hi-Z
Data (input)
Hi-Z
Low-order address (output)
Hi-Z
tHRID
ASTB (Output) tHSTA tFRA RD (Output) tDSTR tDRID tDAR tWRL tDSTWTH tHSTWT tDSTWT tDRWT tDAWT WAIT (Input) tHRWT tDRWTH tDRA
72
PD784054(A)
Write Operation (8 bits)
tCYK (CLK)
AD8-AD15 (Output) tSAST Low-order address (Output) tWSTH ASTB (Output) tHSTA LWR (Output) tDSTW
High-order address
High-order address
AD0-AD7 (Output)
Undefined
Data (Output) tHWOD
Low-order address (Output)
tDWST
tDWOD tDAW tDSTWTH tHSTWT tDSTWT tDWWT tWWL
tSODW
tHWWT tDWWTH
tDAWT WAIT (Input)
73
PD784054(A)
Read Operation (16 bits)
tCYK (CLK)
tSAST AD8-AD15 AD0-AD7 (Input/output) Hi-Z
tDAID Hi-Z Data (Input) Hi-Z Address (Output) Hi-Z
Address (Output) tWSTH
tHRID
ASTB (Output) tHSTA tFRA RD (Output) tDSTR tDRID tDAR tDSTWTH tHSTWT tDSTWT tDRWT tDAWT WAIT (Input) tHRWT tDRWTH tWRL tDRA
74
PD784054(A)
Write Operation (16 bits)
tCYK (CLK)
AD8-AD15 AD0-AD7 (Output)
tSAST Address (Output) tWSTH Undefined Data (Output) tHWOD Address (Output)
ASTB (Output) tHSTA HWR, LWR (Output) tDSTW tDWOD tDAW tDSTWTH tHSTWT tDSTWT tDWWT tHWWT tDWWTH tWWL tSODW tDWST
tDAWT WAIT (Input)
75
PD784054(A)
Serial Operation
tCYSK tWSKL SCK1, SCK2 tDSBSK SO1, SO2 tWSKH
SI1, SI2 tSSSK tHSSK
Interrupt Input Timing
tWNIH tWNIL
0.8 VDD NMI 0.8 V
tWITH
tWITL
0.8 VDD INTP0-INTP6 0.8 V
Reset Input Timing
tWRSH tWRSL
0.8 VDD RESET 0.8 V
76
PD784054(A)
14. PACKAGE DRAWING
80 PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end
CD
S Q R
80 1
21 20
F G H P I
M
J K M N L
NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 17.20.4 14.00.2 14.00.2 17.20.4 0.825 0.825 0.300.10 0.13 0.65 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX.
INCHES 0.6770.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 +0.005 -0.004 0.0040.004 55 0.119 MAX. S80GC-65-3B9-5
Remark The package dimensions and materials of ES versions are the same as those of mass-production versions.
77
PD784054(A)
15. RECOMMENDED SOLDERING CONDITIONS
These products should be soldered and mounted under the conditions recommended below. For details of soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, please contact your NEC representative. Table 15-1. Surface-Mount Type Soldering Conditions
PD784054GC(A)-xxx-3B9 : 80-pin plastic QFP (14 x 14 mm) PD784054GC(A1)-xxx-3B9 : 80-pin plastic QFP (14 x 14 mm) PD784054GC(A2)-xxx-3B9 : 80-pin plastic QFP (14 x 14 mm)
Recommended Condition Symbol IR35-00-3 -
Soldering Method Infrared reflow Partial heating
Soldering Conditions Package peak temperature: 235 C, Time: 30 sec. max. (210 C min.), Number of times: 3 max. Pin temperature: 300 C max., 3 sec. max. (per side of device)
78
PD784054(A)
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for developing systems using the PD784054(A). Refer to (5) Cautions when the development tools are used (1) Language processing software
RA78K4 CC78K4 DF784046 CC78K4-L 78K/IV series common assembler package 78K/IV series common C compiler package Device file commonly used with the PD784046 subseries 78K/IV series common C compiler library source file
(2) Flash memory writing tools
Flashpro II (Part number: FL-PR2) FA-80GC Dedicated flash programmer for microcomputers incorporating flash memory Adapter for flash memory writing
(3) Debugging tools * When using the IE-78K4-NS in-circuit emulator
IE78K4-NS Note IE-70000-MC-PS-B IE-70000-98-IF-C Note IE-70000-CD-IF Note IE-70000-PC-IF-C Note IE-784046-NS-EM1 Note NP-80GC EV-9200GC-80 ID78K4-NS Note SM78K4 DF784046 78K/IV series common in-circuit emulator Power supply unit for IE-78K4-NS Interface adapter necessary when a PC-9800 series computer (except notebook-type personal computer) is used as host machine PC card and interface cable necessary when a PC-9800 series notebook-type personal computer is used as host machine Interface adapter necessary when an IBM PC/ATTM or a compatible machine is used as host machine Emulation board for emulating the PD784054(A) subseries Emulation probe for 80-pin plastic QFP (GC-3B9 type) Socket to be mounted on the board of the target system for 80-pin plastic QFP (GC-3B9 type) Integrated debugger for IE-78K4-NS 78K/IV series common system simulator Device file commonly used with the PD784046 subseries
Note
Under development
79
PD784054(A)
* When using the IE-784000-R in-circuit emulator
IE-784000-R IE-70000-98-IF-B IE-70000-98-IF-C Note IE-70000-98N-IF IE-70000-PC-IF-B IE-70000-PC-IF-C Note IE-78000-R-SV3 IE-784000-R-EM IE-784046-NS-EM1 Note IE-784046-R-EM1 IE78K4-R-EX2 Note EP-78230GC-R EV-9200GC-80 ID78K4 SM78K4 DF784046 78K/IV series common in-circuit emulator Interface adapter necessary when a PC-9800 series computer (except notebook-type personal computer) is used as host machine Interface adapter and cable necessary when a PC-9800 series notebook-type personal computer is used as host machine Interface adapter necessary when an IBM PC/AT or a compatible machine is used as host machine Interface adapter and cable necessary when an EWS is used as host machine 78K/IV series common emulation board Emulation board for emulating the PD784054(A) Emulation probe conversion board necessary when the IE-784046-NS-EM1 is used in the IE-784000-R. Not necessary when the IE-784046-R-EM1 is used. Emulation probe for 80-pin plastic QFP (GC-3B9 type) Socket to be mounted on the board of the target system made for the 80-pin plastic QFP (GC-3B9 type) Integrated debugger for IE-784000-R 78K/IV series common system simulator Device file commonly used with the PD784046 subseries
Note Under development (4) Real-time OS
RX78K/IV MX78K4 Real-time OS for 78K/IV series OS for 78K/IV series
80
PD784054(A)
(5) Cautions when the development tools are used * The ID-78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784046. * The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784046. * Flashpro II, FA-80GC, and NP-80GC are product of Naito Densei Machida Mfg. Co., Ltd. (TEL: (044)8223813). Contact an NEC distributor when purchasing these products. * Host machines and OSs compatible with the software are as follows:
Host Machine [OS] PC PC-9800 Series IBM PC/AT and compatible machines [Japanese/English Windows]
Note Note
EWS HP9000 series 700 TM [HP-UX TM] SPARCstation TM [SunOS TM] NEWSTM (RISC) [NEWS-OS TM ]
[Windows TM ]
Software RA78K4 CC78K4 ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4
-
-
Note Note
Note
DOS based software
81
PD784054(A)
APPENDIX B. RELATED DOCUMENTS
Device-related documents
Document Japanese Document No. English This document U11447E U11719E - U10905E - - U10095E
PD784054(A) Data Sheet PD78F4046 Preliminary Product Information PD784054 User's Manual - Hardware PD784054 Special Function Register Table
78K/IV Series User's Manual - Instruction 78K/IV Series Instruction Table 78K/IV Series Instruction Set 78K/IV Series Application Note - Software Basics
U13122J U11447J U11719J U11113J U10905J U10594J U10595J U10095J
Development tool-related documents (User's Manuals)
Document Japanese RA78K4 Assembler Package Operation Language RA78K4 Structured Assembler Preprocessor CC78K4 C Compiler Operation Language CC78K Series Library Source File IE-78K4-NS IE-784000-R IE-784046-NS-EM1 IE-784046-R-EM1 EP-78230 SM78K4 System Simulator Windows Based SM78K Series System Simulator ID78K4-NS Integrated Debugger ID78K4 Integrated Debugger Windows Based ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Based Reference U11334J U11162J U11743J U11572J EEU-961 U12322J On preparation U12903J Planned U11677J EEU-985 U10093J Planned EEU-1534 Planned U11677E EEU-1515 U10093E U10092E U12796E U10440E U11960E Document No. English U11334E U11162E U11743E U11572E U11571E -
External Part User Open U10092J Interface Specifications Reference Reference Reference U12796J U10440J U11960J
Caution
The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of the document when designing your system.
82
PD784054(A)
Embedded software-related documents (User's Manuals)
Document Japanese 78K/IV Series Real-Time OS Fundamental Installation Debugger 78K/IV Series OS MX78K4 Fundamental U10603J U10604J U10364J U11779J Document No. English U10603E U10604E - -
Other documents
Document Japanese IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability and Quality Control Guide to Prevent Damages for Semiconductor Devices by Electrostatic Discharge (ESD) Semiconductor Quality/Reliability Handbook Microcontroller-Related Product Guide - Third Parties C10943X C10535J C11531J C10983J C11892J C12769J U11416J C10535E C11531E C10983E C11892E - - Document No. English
Caution
The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of the document when designing your system.
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PD784054(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829
J97. 8
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PD784054(A)
IEBus is a trademark of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of IBM Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation.
Some of related document may be preliminary, but is not marked as such. Please keep this in mind as you refer to this information The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
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